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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02002/*
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02005 */
6
Simon Glassfb6f4822020-02-03 07:36:17 -07007#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +02009#include <dm.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <asm/cache.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020012#include <asm/io.h>
13#include <dm/platform_data/serial_pl01x.h>
14#include <asm/arch/hi3798cv200.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020015#include <asm/armv8/mmu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020018
19DECLARE_GLOBAL_DATA_PTR;
20
21static struct mm_region poplar_mem_map[] = {
22 {
23 .virt = 0x0UL,
24 .phys = 0x0UL,
25 .size = 0x80000000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
27 PTE_BLOCK_INNER_SHARE
28 }, {
29 .virt = 0x80000000UL,
30 .phys = 0x80000000UL,
31 .size = 0x80000000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
33 PTE_BLOCK_NON_SHARE |
34 PTE_BLOCK_PXN | PTE_BLOCK_UXN
35 }, {
36 0,
37 }
38};
39
40struct mm_region *mem_map = poplar_mem_map;
41
Shawn Guo9bbb50d2018-12-12 15:24:44 +080042#if !CONFIG_IS_ENABLED(OF_CONTROL)
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020043static const struct pl01x_serial_platdata serial_platdata = {
44 .base = REG_BASE_UART0,
45 .type = TYPE_PL010,
46 .clock = 75000000,
47};
48
49U_BOOT_DEVICE(poplar_serial) = {
50 .name = "serial_pl01x",
51 .platdata = &serial_platdata,
52};
Shawn Guo9bbb50d2018-12-12 15:24:44 +080053#endif
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +020054
55int checkboard(void)
56{
57 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
58
59 return 0;
60}
61
62void reset_cpu(ulong addr)
63{
64 psci_system_reset();
65}
66
67int dram_init(void)
68{
69 gd->ram_size = get_ram_size(NULL, 0x80000000);
70
71 return 0;
72}
73
74/*
75 * Some linux kernel versions don't use memory before its load address, so to
76 * be generic we just pretend it isn't there. In previous uboot versions we
77 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
78 * could persist in memory and be left alone by the kernel.
79 *
80 * That led to a problem when mapping memory in older kernels. That PSCI code
81 * now lies in memory below the kernel load offset; it therefore won't be
82 * touched by the kernel, and by not specially reserving it we avoid the mapping
83 * problem as well.
84 *
85 */
86#define KERNEL_TEXT_OFFSET 0x00080000
87
88int dram_init_banksize(void)
89{
90 gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
91 gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
92
93 return 0;
94}
95
96static void usb2_phy_config(void)
97{
98 const u32 config[] = {
99 /* close EOP pre-emphasis. open data pre-emphasis */
100 0xa1001c,
101 /* Rcomp = 150mW, increase DC level */
102 0xa00607,
103 /* keep Rcomp working */
104 0xa10700,
105 /* Icomp = 212mW, increase current drive */
106 0xa00aab,
107 /* EMI fix: rx_active not stay 1 when error packets received */
108 0xa11140,
109 /* Comp mode select */
110 0xa11041,
111 /* adjust eye diagram */
112 0xa0098c,
113 /* adjust eye diagram */
114 0xa10a0a,
115 };
116 int i;
117
118 for (i = 0; i < ARRAY_SIZE(config); i++) {
119 writel(config[i], PERI_CTRL_USB0);
120 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
121 udelay(20);
122 }
123}
124
125static void usb2_phy_init(void)
126{
127 /* reset usb2 controller bus/utmi/roothub */
128 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
129 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
130 udelay(200);
131
132 /* reset usb2 phy por/utmi */
133 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
134 udelay(200);
135
136 /* open usb2 ref clk */
137 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
138 udelay(300);
139
140 /* cancel usb2 power on reset */
141 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
142 udelay(500);
143
144 usb2_phy_config();
145
146 /* cancel usb2 port reset, wait comp circuit stable */
147 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
148 mdelay(10);
149
150 /* open usb2 controller clk */
151 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
152 USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
153 USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
154 udelay(200);
155
156 /* cancel usb2 control reset */
157 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
158 USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
159 udelay(200);
160}
161
Shawn Guo0f56fde2018-12-18 17:52:06 +0800162#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
Simon Glass0af6e2d2019-08-01 09:46:52 -0600163#include <env.h>
Shawn Guo0f56fde2018-12-18 17:52:06 +0800164#include <usb.h>
165#include <usb/dwc2_udc.h>
166#include <g_dnl.h>
167
168static struct dwc2_plat_otg_data poplar_otg_data = {
169 .regs_otg = HIOTG_BASE_ADDR
170};
171
172static void set_usb_to_device(void)
173{
174 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
175}
176
177int board_usb_init(int index, enum usb_init_type init)
178{
179 set_usb_to_device();
180 return dwc2_udc_probe(&poplar_otg_data);
181}
182
183int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
184{
185 if (!env_get("serial#"))
186 g_dnl_set_serialnumber("0123456789POPLAR");
187 return 0;
188}
189#endif
190
Jorge Ramirez-Ortizf5b38422017-06-26 15:52:49 +0200191int board_init(void)
192{
193 usb2_phy_init();
194
195 return 0;
196}
197