blob: c8907bccec5d5eab3d5bba6e55397885a713c9fe [file] [log] [blame]
Trevor Woerner513f6402020-05-06 08:02:41 -04001if ARCH_TEGRA
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09002
Simon Glass035939e2021-07-10 21:14:30 -06003config SPL_GPIO
Simon Glass0bdfc3e2016-09-12 23:18:39 -06004 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glassf4d60392021-08-08 12:20:12 -060012config SPL_SERIAL
Simon Glasse076d6f2016-09-12 23:18:56 -060013 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Svyatoslav Ryhel7d5a2f42023-02-14 19:35:35 +020018config TEGRA_CRYPTO
19 bool "Tegra AES128 crypto module"
20 select AES
Svyatoslav Ryhel7d5a2f42023-02-14 19:35:35 +020021
Thierry Redingc3598a42019-04-15 11:32:19 +020022config TEGRA_GP_PADCTRL
23 bool
24
Stephen Warrenadf3abd2016-07-18 12:17:11 -060025config TEGRA_IVC
26 bool "Tegra IVC protocol"
27 help
28 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
29 (Inter Processor Communication) framework. Within the context of
30 U-Boot, it is typically used for communication between the main CPU
31 and various auxiliary processors.
32
Thierry Reding17987bb2019-04-15 11:32:20 +020033config TEGRA_MC
34 bool
35
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020036config TEGRA_PMC
37 bool
38
Thierry Redingce7eb162019-04-15 11:32:25 +020039config TEGRA_PMC_SECURE
40 bool
41 depends on TEGRA_PMC
42
Stephen Warren8c29e652015-11-23 10:32:01 -070043config TEGRA_COMMON
44 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020045 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060046 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070047 select DM
Tom Warren7b5002e2015-07-17 08:12:51 -070048 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070049 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060050 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060051 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070052 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060053 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070054 select DM_SERIAL
55 select DM_SPI
56 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060057 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070058 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020059 select SPI
Svyatoslav Ryhel4936bad2023-10-24 10:49:04 +030060 select SYSRESET
Svyatoslav Ryhel4936bad2023-10-24 10:49:04 +030061 select SYSRESET_TEGRA
Michal Simek2e7c8192018-07-23 15:55:14 +020062 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010063 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070064
Stephen Warren905752c2016-09-13 10:46:00 -060065config TEGRA_NO_BPMP
66 bool "Tegra common options for SoCs without BPMP"
67 select TEGRA_CAR
68 select TEGRA_CAR_CLOCK
69 select TEGRA_CAR_RESET
70
Stephen Warren8c29e652015-11-23 10:32:01 -070071config TEGRA_ARMV7_COMMON
72 bool "Tegra 32-bit common options"
Simon Glassa0c32762020-07-19 13:56:00 -060073 select BINMAN
Lokesh Vutla81b1a672018-04-26 18:21:26 +053074 select CPU_V7A
Svyatoslav Ryhel13961102023-11-27 11:54:21 +020075 select PINCTRL
76 select PINCTRL_TEGRA
Stephen Warren8c29e652015-11-23 10:32:01 -070077 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080078 select SPL_BOARD_INIT if SPL
Svyatoslav Ryhel2447ff12023-12-01 13:22:00 +020079 select SPL_DM if SPL
Svyatoslav Ryhel13961102023-11-27 11:54:21 +020080 select SPL_PINCTRL if SPL
81 select SPL_PINCTRL_TEGRA if SPL
Tom Rinie1e85442021-08-27 21:18:30 -040082 select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
Svyatoslav Ryhel2447ff12023-12-01 13:22:00 +020083 select SPL_SYSRESET if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070084 select SUPPORT_SPL
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +020085 select TIMER
Thierry Reding45ad0b02019-04-15 11:32:18 +020086 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070087 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060088 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020089 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +020090 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -060091 select TEGRA_NO_BPMP
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020092 select TEGRA_PMC
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +020093 select TEGRA_TIMER
Stephen Warren8c29e652015-11-23 10:32:01 -070094
95config TEGRA_ARMV8_COMMON
96 bool "Tegra 64-bit common options"
97 select ARM64
Masahiro Yamadabf4645c2019-06-26 13:51:46 +090098 select INIT_SP_RELATIVE
Stephen Warreneab36052018-01-03 14:31:52 -070099 select LINUX_KERNEL_IMAGE_HEADER
Thierry Reding29ce1d02019-04-15 11:32:32 +0200100 select POSITION_INDEPENDENT
Stephen Warren8c29e652015-11-23 10:32:01 -0700101 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -0700102
Stephen Warreneab36052018-01-03 14:31:52 -0700103if TEGRA_ARMV8_COMMON
104config LNX_KRNL_IMG_TEXT_OFFSET_BASE
105 default 0x80000000
106endif
107
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900108choice
109 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500110 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900111
112config TEGRA20
113 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500114 select ARM_ERRATA_716044
115 select ARM_ERRATA_742230
116 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700117 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900118
119config TEGRA30
120 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500121 select ARM_ERRATA_743622
122 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700123 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900124
125config TEGRA114
126 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700127 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900128
129config TEGRA124
130 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700131 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600132 imply REGMAP
133 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900134
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700135config TEGRA210
136 bool "Tegra210 family"
Tom Rini249f11f2021-08-19 14:19:39 -0400137 select GICV2
Svyatoslav Ryhel13961102023-11-27 11:54:21 +0200138 select PINCTRL
139 select PINCTRL_TEGRA
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +0200140 select TIMER
Stephen Warren8c29e652015-11-23 10:32:01 -0700141 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200142 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200143 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200144 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +0200145 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -0600146 select TEGRA_NO_BPMP
Thierry Reding8ffbcfc2019-04-15 11:32:22 +0200147 select TEGRA_PMC
Thierry Redingce7eb162019-04-15 11:32:25 +0200148 select TEGRA_PMC_SECURE
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +0200149 select TEGRA_TIMER
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700150
Stephen Warren03667eb2016-05-12 13:32:55 -0600151config TEGRA186
152 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600153 select DM_MAILBOX
Tom Rini249f11f2021-08-19 14:19:39 -0400154 select GICV2
Stephen Warrena2148922016-08-08 09:41:34 -0600155 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600156 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600157 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600158 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600159 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600160 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600161 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600162
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900163endchoice
164
Stephen Warren5a44ab42016-01-26 10:59:42 -0700165config TEGRA_DISCONNECT_UDC_ON_BOOT
166 bool "Disconnect USB device mode controller on boot"
Thierry Reding4e9260c2019-04-15 11:32:26 +0200167 depends on CI_UDC
Stephen Warren5a44ab42016-01-26 10:59:42 -0700168 default y
169 help
170 When loading U-Boot into RAM over USB protocols using tools such as
171 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
172 mode controller is initialized and enumerated by the host PC running
173 the tool. Unfortunately, these tools do not shut down the USB
174 controller before executing the downloaded code, and so the host PC
175 does not "de-enumerate" the USB device. This option shuts down the
176 USB controller when U-Boot boots to avoid leaving a stale USB device
177 present.
178
Svyatoslav Ryheld47c7332023-12-11 11:29:40 +0200179config TEGRA_SUPPORT_NON_SECURE
180 bool "Support executing U-Boot in non-secure (NS) mode"
Svyatoslav Ryhel0f6268c2023-12-11 11:37:07 +0200181 depends on TEGRA114 || TEGRA124
Svyatoslav Ryheld47c7332023-12-11 11:29:40 +0200182 help
183 Certain impossible actions will be skipped if the CPU is in NS mode,
184 such as ARM architectural timer initialization.
185
Tom Rinid8d1fb62022-03-30 18:07:13 -0400186config CI_UDC_HAS_HOSTPC
187 def_bool y
188 depends on CI_UDC && !TEGRA20
189
Simon Glass838723b2015-02-11 16:32:59 -0700190config SYS_MALLOC_F_LEN
191 default 0x1800
192
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900193source "arch/arm/mach-tegra/tegra20/Kconfig"
194source "arch/arm/mach-tegra/tegra30/Kconfig"
195source "arch/arm/mach-tegra/tegra114/Kconfig"
196source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700197source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600198source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900199
Tom Rini4b3e7c02022-12-02 16:42:45 -0500200config TEGRA_SPI
201 def_bool y
202 depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI
203
204choice
205 prompt "UART to use for console"
Svyatoslav Ryhel13961102023-11-27 11:54:21 +0200206 depends on PINCTRL_TEGRA
Tom Rini4b3e7c02022-12-02 16:42:45 -0500207 default TEGRA_ENABLE_UARTA
208
209config TEGRA_ENABLE_UARTA
210 bool "Use UARTA"
211
212config TEGRA_ENABLE_UARTB
213 bool "Use UARTB"
214
215config TEGRA_ENABLE_UARTC
216 bool "Use UARTC"
217
218config TEGRA_ENABLE_UARTD
219 bool "Use UARTD"
220
221endchoice
222
Tom Rini4dbaf6f2022-06-08 08:24:33 -0400223config TEGRA_GPU
224 bool "Enable setting up the GPU"
225 depends on TEGRA124 || TEGRA210
226
Simon Glassbd74b032017-05-17 03:25:11 -0600227config CMD_ENTERRCM
228 bool "Enable 'enterrcm' command"
229 default y
230 help
231 Tegra's boot ROM supports a mode whereby code may be downloaded and
232 flash-programmed over a USB connection. On dev boards, this is
233 typically entered by holding down a "force recovery" button and
234 resetting the CPU. However, not all boards have such a button (one
235 example is the Compulab Trimslice), so a method to enter RCM from
236 software is useful.
237
238 Even on boards other than Trimslice, controlling this over a UART
239 may be useful, e.g. to allow simple remote control without the need
240 for mechanical button actuators, or hooking up relays/... to the
241 button.
242
Ramin Khonsarif2f708d2023-02-14 19:35:37 +0200243config CMD_EBTUPDATE
244 bool "Enable 'ebtupdate' command"
Svyatoslav Ryhelf8700e42023-02-14 19:35:38 +0200245 depends on TEGRA20 || TEGRA30
Ramin Khonsarif2f708d2023-02-14 19:35:37 +0200246 select TEGRA_CRYPTO
247 help
248 Updating u-boot from within u-boot in rather complex or even
249 impossible on production devices. To make it easier procedure of
250 re-cryption was created. If your device was re-crypted choose Y.
251
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900252endif