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Dave Liua46daea2006-11-03 19:33:44 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
Dave Liua46daea2006-11-03 19:33:44 -06003 * Dave Liu <daveliu@freescale.com>
Dave Liua46daea2006-11-03 19:33:44 -06004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <common.h>
15#include <ioports.h>
16#include <mpc83xx.h>
17#include <i2c.h>
18#include <spd.h>
19#include <miiphy.h>
Dave Liua46daea2006-11-03 19:33:44 -060020#if defined(CONFIG_PCI)
21#include <pci.h>
22#endif
23#if defined(CONFIG_SPD_EEPROM)
24#include <spd_sdram.h>
25#else
26#include <asm/mmu.h>
27#endif
Kim Phillips774e1b52006-11-01 00:10:40 -060028#if defined(CONFIG_OF_FLAT_TREE)
29#include <ft_build.h>
Jerry Van Baren1a96f622007-07-04 21:27:30 -040030#elif defined(CONFIG_OF_LIBFDT)
Gerald Van Barend6abef42007-03-31 12:23:51 -040031#include <libfdt.h>
Gerald Van Barend6abef42007-03-31 12:23:51 -040032#endif
Dave Liua46daea2006-11-03 19:33:44 -060033
Dave Liue732e9c2006-11-03 12:11:15 -060034const qe_iop_conf_t qe_iop_conf_tab[] = {
35 /* GETH1 */
36 {0, 3, 1, 0, 1}, /* TxD0 */
37 {0, 4, 1, 0, 1}, /* TxD1 */
38 {0, 5, 1, 0, 1}, /* TxD2 */
39 {0, 6, 1, 0, 1}, /* TxD3 */
40 {1, 6, 1, 0, 3}, /* TxD4 */
41 {1, 7, 1, 0, 1}, /* TxD5 */
42 {1, 9, 1, 0, 2}, /* TxD6 */
43 {1, 10, 1, 0, 2}, /* TxD7 */
44 {0, 9, 2, 0, 1}, /* RxD0 */
45 {0, 10, 2, 0, 1}, /* RxD1 */
46 {0, 11, 2, 0, 1}, /* RxD2 */
47 {0, 12, 2, 0, 1}, /* RxD3 */
48 {0, 13, 2, 0, 1}, /* RxD4 */
49 {1, 1, 2, 0, 2}, /* RxD5 */
50 {1, 0, 2, 0, 2}, /* RxD6 */
51 {1, 4, 2, 0, 2}, /* RxD7 */
52 {0, 7, 1, 0, 1}, /* TX_EN */
53 {0, 8, 1, 0, 1}, /* TX_ER */
54 {0, 15, 2, 0, 1}, /* RX_DV */
55 {0, 16, 2, 0, 1}, /* RX_ER */
56 {0, 0, 2, 0, 1}, /* RX_CLK */
57 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
58 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
59 /* GETH2 */
60 {0, 17, 1, 0, 1}, /* TxD0 */
61 {0, 18, 1, 0, 1}, /* TxD1 */
62 {0, 19, 1, 0, 1}, /* TxD2 */
63 {0, 20, 1, 0, 1}, /* TxD3 */
64 {1, 2, 1, 0, 1}, /* TxD4 */
65 {1, 3, 1, 0, 2}, /* TxD5 */
66 {1, 5, 1, 0, 3}, /* TxD6 */
67 {1, 8, 1, 0, 3}, /* TxD7 */
68 {0, 23, 2, 0, 1}, /* RxD0 */
69 {0, 24, 2, 0, 1}, /* RxD1 */
70 {0, 25, 2, 0, 1}, /* RxD2 */
71 {0, 26, 2, 0, 1}, /* RxD3 */
72 {0, 27, 2, 0, 1}, /* RxD4 */
73 {1, 12, 2, 0, 2}, /* RxD5 */
74 {1, 13, 2, 0, 3}, /* RxD6 */
75 {1, 11, 2, 0, 2}, /* RxD7 */
76 {0, 21, 1, 0, 1}, /* TX_EN */
77 {0, 22, 1, 0, 1}, /* TX_ER */
78 {0, 29, 2, 0, 1}, /* RX_DV */
79 {0, 30, 2, 0, 1}, /* RX_ER */
80 {0, 31, 2, 0, 1}, /* RX_CLK */
81 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
82 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
83
84 {0, 1, 3, 0, 2}, /* MDIO */
85 {0, 2, 1, 0, 1}, /* MDC */
86
87 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
88};
89
Dave Liua46daea2006-11-03 19:33:44 -060090int board_early_init_f(void)
91{
Kim Phillips7a1e91b2007-02-14 19:50:53 -060092
93 u8 *bcsr = (u8 *)CFG_BCSR;
94 const immap_t *immr = (immap_t *)CFG_IMMR;
Dave Liua46daea2006-11-03 19:33:44 -060095
96 /* Enable flash write */
97 bcsr[0xa] &= ~0x04;
98
Kim Phillips7a1e91b2007-02-14 19:50:53 -060099 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
100 if (immr->sysconf.spridr == SPR_8360_REV20 ||
Lee Nipperf600cf32007-06-14 20:07:33 -0500101 immr->sysconf.spridr == SPR_8360E_REV20 ||
102 immr->sysconf.spridr == SPR_8360_REV21 ||
103 immr->sysconf.spridr == SPR_8360E_REV21)
Kim Phillips7a1e91b2007-02-14 19:50:53 -0600104 bcsr[0xe] = 0x30;
105
Dave Liua46daea2006-11-03 19:33:44 -0600106 return 0;
107}
108
109#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
110extern void ddr_enable_ecc(unsigned int dram_size);
111#endif
112int fixed_sdram(void);
113void sdram_init(void);
114
115long int initdram(int board_type)
116{
Timur Tabi386a2802006-11-03 12:00:28 -0600117 volatile immap_t *im = (immap_t *) CFG_IMMR;
Dave Liua46daea2006-11-03 19:33:44 -0600118 u32 msize = 0;
119
120 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
121 return -1;
122
123 /* DDR SDRAM - Main SODIMM */
124 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
125#if defined(CONFIG_SPD_EEPROM)
126 msize = spd_sdram();
127#else
128 msize = fixed_sdram();
129#endif
130
131#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
132 /*
133 * Initialize DDR ECC byte
134 */
135 ddr_enable_ecc(msize * 1024 * 1024);
136#endif
137 /*
138 * Initialize SDRAM if it is on local bus.
139 */
140 sdram_init();
141 puts(" DDR RAM: ");
142 /* return total bus SDRAM size(bytes) -- DDR */
143 return (msize * 1024 * 1024);
144}
145
146#if !defined(CONFIG_SPD_EEPROM)
147/*************************************************************************
148 * fixed sdram init -- doesn't use serial presence detect.
149 ************************************************************************/
150int fixed_sdram(void)
151{
Timur Tabi386a2802006-11-03 12:00:28 -0600152 volatile immap_t *im = (immap_t *) CFG_IMMR;
Dave Liua46daea2006-11-03 19:33:44 -0600153 u32 msize = 0;
154 u32 ddr_size;
155 u32 ddr_size_log2;
156
157 msize = CFG_DDR_SIZE;
158 for (ddr_size = msize << 20, ddr_size_log2 = 0;
159 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
160 if (ddr_size & 1) {
161 return -1;
162 }
163 }
164 im->sysconf.ddrlaw[0].ar =
165 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
166#if (CFG_DDR_SIZE != 256)
167#warning Currenly any ddr size other than 256 is not supported
168#endif
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800169#ifdef CONFIG_DDR_II
170 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
171 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
172 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
173 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
174 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
175 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
176 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
177 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
178 im->ddr.sdram_mode = CFG_DDR_MODE;
179 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
180 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
181 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
182#else
Dave Liua46daea2006-11-03 19:33:44 -0600183 im->ddr.csbnds[0].csbnds = 0x00000007;
184 im->ddr.csbnds[1].csbnds = 0x0008000f;
185
186 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
187 im->ddr.cs_config[1] = CFG_DDR_CONFIG;
188
189 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
190 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
191 im->ddr.sdram_cfg = CFG_DDR_CONTROL;
192
193 im->ddr.sdram_mode = CFG_DDR_MODE;
194 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800195#endif
Dave Liua46daea2006-11-03 19:33:44 -0600196 udelay(200);
197 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
198
199 return msize;
200}
201#endif /*!CFG_SPD_EEPROM */
202
203int checkboard(void)
204{
205 puts("Board: Freescale MPC8360EMDS\n");
206 return 0;
207}
208
209/*
210 * if MPC8360EMDS is soldered with SDRAM
211 */
212#if defined(CFG_BR2_PRELIM) \
213 && defined(CFG_OR2_PRELIM) \
214 && defined(CFG_LBLAWBAR2_PRELIM) \
215 && defined(CFG_LBLAWAR2_PRELIM)
216/*
217 * Initialize SDRAM memory on the Local Bus.
218 */
219
220void sdram_init(void)
221{
Timur Tabi386a2802006-11-03 12:00:28 -0600222 volatile immap_t *immap = (immap_t *) CFG_IMMR;
Dave Liua46daea2006-11-03 19:33:44 -0600223 volatile lbus83xx_t *lbc = &immap->lbus;
224 uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
225
226 puts("\n SDRAM on Local Bus: ");
227 print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
228 /*
229 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
230 */
231 /*setup mtrpt, lsrt and lbcr for LB bus */
232 lbc->lbcr = CFG_LBC_LBCR;
233 lbc->mrtpr = CFG_LBC_MRTPR;
234 lbc->lsrt = CFG_LBC_LSRT;
235 asm("sync");
236
237 /*
238 * Configure the SDRAM controller Machine Mode Register.
239 */
240 lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
241 lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
242 asm("sync");
243 *sdram_addr = 0xff;
244 udelay(100);
245
246 /*
247 * We need do 8 times auto refresh operation.
248 */
249 lbc->lsdmr = CFG_LBC_LSDMR_2;
250 asm("sync");
251 *sdram_addr = 0xff; /* 1 times */
252 udelay(100);
253 *sdram_addr = 0xff; /* 2 times */
254 udelay(100);
255 *sdram_addr = 0xff; /* 3 times */
256 udelay(100);
257 *sdram_addr = 0xff; /* 4 times */
258 udelay(100);
259 *sdram_addr = 0xff; /* 5 times */
260 udelay(100);
261 *sdram_addr = 0xff; /* 6 times */
262 udelay(100);
263 *sdram_addr = 0xff; /* 7 times */
264 udelay(100);
265 *sdram_addr = 0xff; /* 8 times */
266 udelay(100);
267
268 /* Mode register write operation */
269 lbc->lsdmr = CFG_LBC_LSDMR_4;
270 asm("sync");
271 *(sdram_addr + 0xcc) = 0xff;
272 udelay(100);
273
274 /* Normal operation */
275 lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
276 asm("sync");
277 *sdram_addr = 0xff;
278 udelay(100);
279}
280#else
281void sdram_init(void)
282{
283 puts("SDRAM on Local Bus is NOT available!\n");
284}
285#endif
286
Gerald Van Barend6abef42007-03-31 12:23:51 -0400287#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
288 && defined(CONFIG_OF_BOARD_SETUP)
Kim Phillips774e1b52006-11-01 00:10:40 -0600289void
290ft_board_setup(void *blob, bd_t *bd)
291{
Kim Phillipsdc0b59d2007-08-15 22:30:26 -0500292#if defined(CONFIG_OF_FLAT_TREE)
Kim Phillips774e1b52006-11-01 00:10:40 -0600293 u32 *p;
294 int len;
295
Kim Phillips774e1b52006-11-01 00:10:40 -0600296 p = ft_get_prop(blob, "/memory/reg", &len);
297 if (p != NULL) {
298 *p++ = cpu_to_be32(bd->bi_memstart);
299 *p = cpu_to_be32(bd->bi_memsize);
300 }
Gerald Van Barend6abef42007-03-31 12:23:51 -0400301#endif
302
303#ifdef CONFIG_PCI
304 ft_pci_setup(blob, bd);
305#endif
306 ft_cpu_setup(blob, bd);
Kim Phillips774e1b52006-11-01 00:10:40 -0600307}
Gerald Van Barenc4a57ea2007-04-06 14:19:43 -0400308#endif /* CONFIG_OF_x */