blob: 9fc3c18ba21ddc1022d595274767a4d1a636eb9f [file] [log] [blame]
Codrin Ciubotariu6abe0782015-01-12 14:08:33 +02001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Driver for the Vitesse VSC9953 L2 Switch
7 */
8
9#include <asm/io.h>
10#include <asm/fsl_serdes.h>
11#include <fm_eth.h>
12#include <asm/fsl_memac.h>
13#include <vsc9953.h>
14
15static struct vsc9953_info vsc9953_l2sw = {
16 .port[0] = VSC9953_PORT_INFO_INITIALIZER(0),
17 .port[1] = VSC9953_PORT_INFO_INITIALIZER(1),
18 .port[2] = VSC9953_PORT_INFO_INITIALIZER(2),
19 .port[3] = VSC9953_PORT_INFO_INITIALIZER(3),
20 .port[4] = VSC9953_PORT_INFO_INITIALIZER(4),
21 .port[5] = VSC9953_PORT_INFO_INITIALIZER(5),
22 .port[6] = VSC9953_PORT_INFO_INITIALIZER(6),
23 .port[7] = VSC9953_PORT_INFO_INITIALIZER(7),
24 .port[8] = VSC9953_PORT_INFO_INITIALIZER(8),
25 .port[9] = VSC9953_PORT_INFO_INITIALIZER(9),
26};
27
28void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus)
29{
30 if (!VSC9953_PORT_CHECK(port))
31 return;
32
33 vsc9953_l2sw.port[port].bus = bus;
34}
35
36void vsc9953_port_info_set_phy_address(int port, int address)
37{
38 if (!VSC9953_PORT_CHECK(port))
39 return;
40
41 vsc9953_l2sw.port[port].phyaddr = address;
42}
43
44void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int)
45{
46 if (!VSC9953_PORT_CHECK(port))
47 return;
48
49 vsc9953_l2sw.port[port].enet_if = phy_int;
50}
51
52void vsc9953_port_enable(int port)
53{
54 if (!VSC9953_PORT_CHECK(port))
55 return;
56
57 vsc9953_l2sw.port[port].enabled = 1;
58}
59
60void vsc9953_port_disable(int port)
61{
62 if (!VSC9953_PORT_CHECK(port))
63 return;
64
65 vsc9953_l2sw.port[port].enabled = 0;
66}
67
68static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr,
69 int regnum, int value)
70{
71 int timeout = 50000;
72
73 out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
74 ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
75 (0x1 << 1));
76 asm("sync");
77
78 while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
79 udelay(1);
80
81 if (timeout == 0)
82 debug("Timeout waiting for MDIO write\n");
83}
84
85static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr,
86 int regnum)
87{
88 int value = 0xFFFF;
89 int timeout = 50000;
90
91 while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout)
92 udelay(1);
93 if (timeout == 0) {
94 debug("Timeout waiting for MDIO operation to finish\n");
95 return value;
96 }
97
98 /* Put the address of the phy, and the register
99 * number into MIICMD
100 */
101 out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
102 ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
103 (0x2 << 1));
104
105 timeout = 50000;
106 /* Wait for the the indication that the read is done */
107 while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
108 udelay(1);
109 if (timeout == 0)
110 debug("Timeout waiting for MDIO read\n");
111
112 /* Grab the value read from the PHY */
113 value = in_le32(&phyregs->miimdata);
114
115 if ((value & 0x00030000) == 0)
116 return value & 0x0000ffff;
117
118 return value;
119}
120
121static int init_phy(struct eth_device *dev)
122{
123 struct vsc9953_port_info *l2sw_port = dev->priv;
124 struct phy_device *phydev = NULL;
125
126#ifdef CONFIG_PHYLIB
127 if (!l2sw_port->bus)
128 return 0;
129 phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev,
130 l2sw_port->enet_if);
131 if (!phydev) {
132 printf("Failed to connect\n");
133 return -1;
134 }
135
136 phydev->supported &= SUPPORTED_10baseT_Half |
137 SUPPORTED_10baseT_Full |
138 SUPPORTED_100baseT_Half |
139 SUPPORTED_100baseT_Full |
140 SUPPORTED_1000baseT_Full;
141 phydev->advertising = phydev->supported;
142
143 l2sw_port->phydev = phydev;
144
145 phy_config(phydev);
146#endif
147
148 return 0;
149}
150
151static int vsc9953_port_init(int port)
152{
153 struct eth_device *dev;
154
155 /* Internal ports never have a PHY */
156 if (VSC9953_INTERNAL_PORT_CHECK(port))
157 return 0;
158
159 /* alloc eth device */
160 dev = (struct eth_device *)calloc(1, sizeof(struct eth_device));
161 if (!dev)
162 return 1;
163
164 sprintf(dev->name, "SW@PORT%d", port);
165 dev->priv = &vsc9953_l2sw.port[port];
166 dev->init = NULL;
167 dev->halt = NULL;
168 dev->send = NULL;
169 dev->recv = NULL;
170
171 if (init_phy(dev)) {
172 free(dev);
173 return 1;
174 }
175
176 return 0;
177}
178
179void vsc9953_init(bd_t *bis)
180{
181 u32 i, hdx_cfg = 0, phy_addr = 0;
182 int timeout;
183 struct vsc9953_system_reg *l2sys_reg;
184 struct vsc9953_qsys_reg *l2qsys_reg;
185 struct vsc9953_dev_gmii *l2dev_gmii_reg;
186 struct vsc9953_analyzer *l2ana_reg;
187 struct vsc9953_devcpu_gcb *l2dev_gcb;
188
189 l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET +
190 VSC9953_DEV_GMII_OFFSET);
191
192 l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
193 VSC9953_ANA_OFFSET);
194
195 l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
196 VSC9953_SYS_OFFSET);
197
198 l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
199 VSC9953_QSYS_OFFSET);
200
201 l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET +
202 VSC9953_DEVCPU_GCB);
203
204 out_le32(&l2dev_gcb->chip_regs.soft_rst,
205 CONFIG_VSC9953_SOFT_SWC_RST_ENA);
206 timeout = 50000;
207 while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) &
208 CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout)
209 udelay(1); /* busy wait for vsc9953 soft reset */
210 if (timeout == 0)
211 debug("Timeout waiting for VSC9953 to reset\n");
212
213 out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE |
214 CONFIG_VSC9953_MEM_INIT);
215
216 timeout = 50000;
217 while ((in_le32(&l2sys_reg->sys.reset_cfg) &
218 CONFIG_VSC9953_MEM_INIT) && --timeout)
219 udelay(1); /* busy wait for vsc9953 memory init */
220 if (timeout == 0)
221 debug("Timeout waiting for VSC9953 memory to initialize\n");
222
223 out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg)
224 | CONFIG_VSC9953_CORE_ENABLE));
225
226 /* VSC9953 Setting to be done once only */
227 out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00);
228
229 for (i = 0; i < VSC9953_MAX_PORTS; i++) {
230 if (vsc9953_port_init(i))
231 printf("Failed to initialize l2switch port %d\n", i);
232
233 /* Enable VSC9953 GMII Ports Port ID 0 - 7 */
234 if (VSC9953_INTERNAL_PORT_CHECK(i)) {
235 out_le32(&l2ana_reg->pfc[i].pfc_cfg,
236 CONFIG_VSC9953_PFC_FC_QSGMII);
237 out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
238 CONFIG_VSC9953_MAC_FC_CFG_QSGMII);
239 } else {
240 out_le32(&l2ana_reg->pfc[i].pfc_cfg,
241 CONFIG_VSC9953_PFC_FC);
242 out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
243 CONFIG_VSC9953_MAC_FC_CFG);
244 }
245 out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
246 CONFIG_VSC9953_CLOCK_CFG);
247 out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
248 CONFIG_VSC9953_MAC_ENA_CFG);
249 out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg,
250 CONFIG_VSC9953_MAC_MODE_CFG);
251 out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg,
252 CONFIG_VSC9953_MAC_IFG_CFG);
253 /* mac_hdx_cfg varies with port id*/
254 hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16));
255 out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg);
256 out_le32(&l2sys_reg->sys.front_port_mode[i],
257 CONFIG_VSC9953_FRONT_PORT_MODE);
258 out_le32(&l2qsys_reg->sys.switch_port_mode[i],
259 CONFIG_VSC9953_PORT_ENA);
260 out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg,
261 CONFIG_VSC9953_MAC_MAX_LEN);
262 out_le32(&l2sys_reg->pause_cfg.pause_cfg[i],
263 CONFIG_VSC9953_PAUSE_CFG);
264 /* WAIT FOR 2 us*/
265 udelay(2);
266
267 l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(
268 (char *)l2dev_gmii_reg
269 + T1040_SWITCH_GMII_DEV_OFFSET);
270
271 /* Initialize Lynx PHY Wrappers */
272 phy_addr = 0;
273 if (vsc9953_l2sw.port[i].enet_if ==
274 PHY_INTERFACE_MODE_QSGMII)
275 phy_addr = (i + 0x4) & 0x1F;
276 else if (vsc9953_l2sw.port[i].enet_if ==
277 PHY_INTERFACE_MODE_SGMII)
278 phy_addr = (i + 1) & 0x1F;
279
280 if (phy_addr) {
281 /* SGMII IF mode + AN enable */
282 vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
283 0x14, PHY_SGMII_IF_MODE_AN |
284 PHY_SGMII_IF_MODE_SGMII);
285 /* Dev ability according to SGMII specification */
286 vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
287 0x4, PHY_SGMII_DEV_ABILITY_SGMII);
288 /* Adjust link timer for SGMII
289 * 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40
290 */
291 vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
292 0x13, 0x0003);
293 vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
294 0x12, 0x0d40);
295 /* Restart AN */
296 vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
297 0x0, PHY_SGMII_CR_DEF_VAL |
298 PHY_SGMII_CR_RESET_AN);
299
300 timeout = 50000;
301 while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0],
302 phy_addr, 0x01) & 0x0020) && --timeout)
303 udelay(1); /* wait for AN to complete */
304 if (timeout == 0)
305 debug("Timeout waiting for AN to complete\n");
306 }
307 }
308
309 printf("VSC9953 L2 switch initialized\n");
310 return;
311}
312
313#ifdef CONFIG_VSC9953_CMD
314/* Enable/disable status of a VSC9953 port */
315static void vsc9953_port_status_set(int port_nr, u8 enabled)
316{
317 u32 val;
318 struct vsc9953_qsys_reg *l2qsys_reg;
319
320 /* Administrative down */
321 if (vsc9953_l2sw.port[port_nr].enabled == 0)
322 return;
323
324 l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
325 VSC9953_QSYS_OFFSET);
326
327 val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]);
328 if (enabled == 1)
329 val |= (1 << 13);
330 else
331 val &= ~(1 << 13);
332
333 out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val);
334}
335
336/* Set all VSC9953 ports' status */
337static void vsc9953_port_all_status_set(u8 enabled)
338{
339 int i;
340
341 for (i = 0; i < VSC9953_MAX_PORTS; i++)
342 vsc9953_port_status_set(i, enabled);
343}
344
345/* Start autonegotiation for a VSC9953 PHY */
346static void vsc9953_phy_autoneg(int port_nr)
347{
348 if (!vsc9953_l2sw.port[port_nr].phydev)
349 return;
350
351 if (vsc9953_l2sw.port[port_nr].phydev->drv->startup(
352 vsc9953_l2sw.port[port_nr].phydev))
353 printf("Failed to start PHY for port %d\n", port_nr);
354}
355
356/* Start autonegotiation for all VSC9953 PHYs */
357static void vsc9953_phy_all_autoneg(void)
358{
359 int i;
360
361 for (i = 0; i < VSC9953_MAX_PORTS; i++)
362 vsc9953_phy_autoneg(i);
363}
364
365/* Print a VSC9953 port's configuration */
366static void vsc9953_port_config_show(int port)
367{
368 int speed;
369 int duplex;
370 int link;
371 u8 enabled;
372 u32 val;
373 struct vsc9953_qsys_reg *l2qsys_reg;
374
375 l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
376 VSC9953_QSYS_OFFSET);
377
378 val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]);
379 enabled = vsc9953_l2sw.port[port].enabled &
380 ((val & 0x00002000) >> 13);
381
382 /* internal ports (8 and 9) are fixed */
383 if (VSC9953_INTERNAL_PORT_CHECK(port)) {
384 link = 1;
385 speed = SPEED_2500;
386 duplex = DUPLEX_FULL;
387 } else {
388 if (vsc9953_l2sw.port[port].phydev) {
389 link = vsc9953_l2sw.port[port].phydev->link;
390 speed = vsc9953_l2sw.port[port].phydev->speed;
391 duplex = vsc9953_l2sw.port[port].phydev->duplex;
392 } else {
393 link = -1;
394 speed = -1;
395 duplex = -1;
396 }
397 }
398
399 printf("%8d ", port);
400 printf("%8s ", enabled == 1 ? "enabled" : "disabled");
401 printf("%8s ", link == 1 ? "up" : "down");
402
403 switch (speed) {
404 case SPEED_10:
405 printf("%8d ", 10);
406 break;
407 case SPEED_100:
408 printf("%8d ", 100);
409 break;
410 case SPEED_1000:
411 printf("%8d ", 1000);
412 break;
413 case SPEED_2500:
414 printf("%8d ", 2500);
415 break;
416 case SPEED_10000:
417 printf("%8d ", 10000);
418 break;
419 default:
420 printf("%8s ", "-");
421 }
422
423 printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half");
424}
425
426/* Print VSC9953 ports' configuration */
427static void vsc9953_port_all_config_show(void)
428{
429 int i;
430
431 for (i = 0; i < VSC9953_MAX_PORTS; i++)
432 vsc9953_port_config_show(i);
433}
434
435/* function to interpret commands starting with "ethsw " */
436static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
437{
438 u8 enable;
439 u32 port;
440
441 if (argc < 4)
442 return -1;
443
444 if (strcmp(argv[1], "port"))
445 return -1;
446
447 if (!strcmp(argv[3], "show")) {
448 if (!strcmp(argv[2], "all")) {
449 vsc9953_phy_all_autoneg();
450 printf("%8s %8s %8s %8s %8s\n",
451 "Port", "Status", "Link", "Speed",
452 "Duplex");
453 vsc9953_port_all_config_show();
454 return 0;
455 } else {
456 port = simple_strtoul(argv[2], NULL, 10);
457 if (!VSC9953_PORT_CHECK(port))
458 return -1;
459 vsc9953_phy_autoneg(port);
460 printf("%8s %8s %8s %8s %8s\n",
461 "Port", "Status", "Link", "Speed",
462 "Duplex");
463 vsc9953_port_config_show(port);
464 return 0;
465 }
466 } else if (!strcmp(argv[3], "enable")) {
467 enable = 1;
468 } else if (!strcmp(argv[3], "disable")) {
469 enable = 0;
470 } else {
471 return -1;
472 }
473
474 if (!strcmp(argv[2], "all")) {
475 vsc9953_port_all_status_set(enable);
476 return 0;
477 } else {
478 port = simple_strtoul(argv[2], NULL, 10);
479 if (!VSC9953_PORT_CHECK(port))
480 return -1;
481 vsc9953_port_status_set(port, enable);
482 return 0;
483 }
484
485 return -1;
486}
487
488U_BOOT_CMD(ethsw, 5, 0, do_ethsw,
489 "vsc9953 l2 switch commands",
490 "port <port_nr> enable|disable\n"
491 " - enable/disable an l2 switch port\n"
492 " port_nr=0..9; use \"all\" for all ports\n"
493 "ethsw port <port_nr> show\n"
494 " - show an l2 switch port's configuration\n"
495 " port_nr=0..9; use \"all\" for all ports\n"
496);
497#endif /* CONFIG_VSC9953_CMD */