blob: c56a87b083b7147647bfd61cb361da37100cec23 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +09002/*
3 * Copyright (C) 2010 Samsung Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Kyungmin Park <kyungmin.park@samsung.com>
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +09006 */
7
8#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06009#include <env.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Piotr Wilczeke372b552012-10-19 05:34:03 +000011#include <spi.h>
Piotr Wilczek461c5e52012-10-19 05:34:07 +000012#include <lcd.h>
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090013#include <asm/io.h>
Piotr Wilczeke372b552012-10-19 05:34:03 +000014#include <asm/gpio.h>
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090015#include <asm/arch/adc.h>
Piotr Wilczek3b179142012-09-20 00:19:59 +000016#include <asm/arch/pinmux.h>
Piotr Wilczek6ce94c32012-09-20 00:20:00 +000017#include <asm/arch/watchdog.h>
Piotr Wilczek461c5e52012-10-19 05:34:07 +000018#include <ld9040.h>
Łukasz Majewski1c6dba12012-11-13 03:21:55 +000019#include <power/pmic.h>
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +010020#include <usb.h>
Marek Vasutf1be9cb2015-12-04 02:51:20 +010021#include <usb/dwc2_udc.h>
Lukasz Majewskibf731262011-12-15 10:32:12 +010022#include <asm/arch/cpu.h>
Łukasz Majewski1c6dba12012-11-13 03:21:55 +000023#include <power/max8998_pmic.h>
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +010024#include <libtizen.h>
Przemyslaw Marczak94df8012014-01-22 11:24:20 +010025#include <samsung/misc.h>
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +010026#include <usb_mass_storage.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060027#include <asm/mach-types.h>
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090028
29DECLARE_GLOBAL_DATA_PTR;
30
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090031unsigned int board_rev;
Jaehoon Chung40195a22017-01-09 14:47:50 +090032static int init_pmic_lcd(void);
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090033
34u32 get_board_rev(void)
35{
36 return board_rev;
37}
38
Jaehoon Chung40195a22017-01-09 14:47:50 +090039int exynos_power_init(void)
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090040{
Jaehoon Chung40195a22017-01-09 14:47:50 +090041 return init_pmic_lcd();
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090042}
43
Jaehoon Chung40195a22017-01-09 14:47:50 +090044static int get_hwrev(void)
Łukasz Majewski11be2832012-11-13 03:22:17 +000045{
Jaehoon Chung40195a22017-01-09 14:47:50 +090046 return board_rev & 0xFF;
Łukasz Majewski11be2832012-11-13 03:22:17 +000047}
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090048
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +090049static unsigned short get_adc_value(int channel)
50{
51 struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
52 unsigned short ret = 0;
53 unsigned int reg;
54 unsigned int loop = 0;
55
56 writel(channel & 0xF, &adc->adcmux);
57 writel((1 << 14) | (49 << 6), &adc->adccon);
58 writel(1000 & 0xffff, &adc->adcdly);
59 writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
60 udelay(10);
61 writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
62 udelay(10);
63
64 do {
65 udelay(1);
66 reg = readl(&adc->adccon);
67 } while (!(reg & (1 << 15)) && (loop++ < 1000));
68
69 ret = readl(&adc->adcdat0) & 0xFFF;
70
71 return ret;
72}
73
Łukasz Majewski61f8b402012-03-26 21:53:48 +000074static int adc_power_control(int on)
75{
Jaehoon Chung40195a22017-01-09 14:47:50 +090076 struct udevice *dev;
Łukasz Majewski61f8b402012-03-26 21:53:48 +000077 int ret;
Jaehoon Chung40195a22017-01-09 14:47:50 +090078 u8 reg;
Łukasz Majewski61f8b402012-03-26 21:53:48 +000079
Jaehoon Chung40195a22017-01-09 14:47:50 +090080 ret = pmic_get("max8998-pmic", &dev);
81 if (ret) {
82 puts("Failed to get MAX8998!\n");
83 return ret;
84 }
Łukasz Majewski61f8b402012-03-26 21:53:48 +000085
Jaehoon Chung40195a22017-01-09 14:47:50 +090086 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
87 if (on)
88 reg |= MAX8998_LDO4;
89 else
90 reg &= ~MAX8998_LDO4;
Łukasz Majewski61f8b402012-03-26 21:53:48 +000091
Jaehoon Chung40195a22017-01-09 14:47:50 +090092 ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
93 if (ret) {
94 puts("MAX8998 LDO setting error\n");
95 return -EINVAL;
96 }
97
Simon Glass7bbb7d92016-11-23 06:34:40 -070098 return 0;
Łukasz Majewski61f8b402012-03-26 21:53:48 +000099}
100
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +0900101static unsigned int get_hw_revision(void)
102{
103 int hwrev, mode0, mode1;
104
Łukasz Majewski61f8b402012-03-26 21:53:48 +0000105 adc_power_control(1);
106
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +0900107 mode0 = get_adc_value(1); /* HWREV_MODE0 */
108 mode1 = get_adc_value(2); /* HWREV_MODE1 */
109
110 /*
111 * XXX Always set the default hwrev as the latest board
112 * ADC = (voltage) / 3.3 * 4096
113 */
114 hwrev = 3;
115
116#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
117 if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
118 hwrev = 0x0; /* 0.01V 0.01V */
119 if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
120 hwrev = 0x1; /* 610mV 0.01V */
121 if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
122 hwrev = 0x2; /* 1.16V 0.01V */
123 if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
124 hwrev = 0x3; /* 1.79V 0.01V */
125#undef IS_RANGE
126
127 debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
128
Łukasz Majewski61f8b402012-03-26 21:53:48 +0000129 adc_power_control(0);
130
Minkyu Kang0aa1a6b2011-01-24 15:33:50 +0900131 return hwrev;
132}
133
134static void check_hw_revision(void)
135{
136 int hwrev;
137
138 hwrev = get_hw_revision();
139
140 board_rev |= hwrev;
141}
142
Lukasz Majewskibf731262011-12-15 10:32:12 +0100143#ifdef CONFIG_USB_GADGET
144static int s5pc210_phy_control(int on)
145{
Jaehoon Chung40195a22017-01-09 14:47:50 +0900146 struct udevice *dev;
147 int ret;
148 u8 reg;
Lukasz Majewskibf731262011-12-15 10:32:12 +0100149
Jaehoon Chung40195a22017-01-09 14:47:50 +0900150 ret = pmic_get("max8998-pmic", &dev);
151 if (ret) {
152 puts("Failed to get MAX8998!\n");
153 return ret;
154 }
Lukasz Majewskibf731262011-12-15 10:32:12 +0100155
156 if (on) {
Jaehoon Chung40195a22017-01-09 14:47:50 +0900157 reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
158 reg |= MAX8998_SAFEOUT1;
159 ret |= pmic_reg_write(dev,
160 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
161
162 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
163 reg |= MAX8998_LDO3;
164 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
165
166 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
167 reg |= MAX8998_LDO8;
168 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
Lukasz Majewskibf731262011-12-15 10:32:12 +0100169
170 } else {
Jaehoon Chung40195a22017-01-09 14:47:50 +0900171 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
172 reg &= ~MAX8998_LDO8;
173 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
174
175 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
176 reg &= ~MAX8998_LDO3;
177 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
178
179 reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
180 reg &= ~MAX8998_SAFEOUT1;
181 ret |= pmic_reg_write(dev,
182 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
Lukasz Majewskibf731262011-12-15 10:32:12 +0100183 }
184
185 if (ret) {
186 puts("MAX8998 LDO setting error!\n");
Jaehoon Chung40195a22017-01-09 14:47:50 +0900187 return -EINVAL;
Lukasz Majewskibf731262011-12-15 10:32:12 +0100188 }
Jaehoon Chung40195a22017-01-09 14:47:50 +0900189
Lukasz Majewskibf731262011-12-15 10:32:12 +0100190 return 0;
191}
192
Marek Vasut6939aca2015-12-04 02:23:29 +0100193struct dwc2_plat_otg_data s5pc210_otg_data = {
Lukasz Majewskibf731262011-12-15 10:32:12 +0100194 .phy_control = s5pc210_phy_control,
195 .regs_phy = EXYNOS4_USBPHY_BASE,
196 .regs_otg = EXYNOS4_USBOTG_BASE,
197 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
198 .usb_flags = PHY0_SLEEP,
199};
200#endif
Piotr Wilczek6ce94c32012-09-20 00:20:00 +0000201
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100202int board_usb_init(int index, enum usb_init_type init)
203{
204 debug("USB_udc_probe\n");
Marek Vasut01b61fa2015-12-04 02:26:33 +0100205 return dwc2_udc_probe(&s5pc210_otg_data);
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100206}
207
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100208int exynos_early_init_f(void)
Piotr Wilczek6ce94c32012-09-20 00:20:00 +0000209{
210 wdt_stop();
211
212 return 0;
213}
Piotr Wilczeke372b552012-10-19 05:34:03 +0000214
Jaehoon Chung40195a22017-01-09 14:47:50 +0900215static int init_pmic_lcd(void)
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000216{
Jaehoon Chung40195a22017-01-09 14:47:50 +0900217 struct udevice *dev;
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000218 unsigned char val;
219 int ret = 0;
220
Jaehoon Chung40195a22017-01-09 14:47:50 +0900221 ret = pmic_get("max8998-pmic", &dev);
222 if (ret) {
223 puts("Failed to get MAX8998 for init_pmic_lcd()!\n");
224 return ret;
225 }
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000226
227 /* LDO7 1.8V */
228 val = 0x02; /* (1800 - 1600) / 100; */
Jaehoon Chung40195a22017-01-09 14:47:50 +0900229 ret |= pmic_reg_write(dev, MAX8998_REG_LDO7, val);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000230
231 /* LDO17 3.0V */
232 val = 0xe; /* (3000 - 1600) / 100; */
Jaehoon Chung40195a22017-01-09 14:47:50 +0900233 ret |= pmic_reg_write(dev, MAX8998_REG_LDO17, val);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000234
235 /* Disable unneeded regulators */
236 /*
237 * ONOFF1
238 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
239 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
240 */
241 val = 0xB9;
Jaehoon Chung40195a22017-01-09 14:47:50 +0900242 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, val);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000243
244 /* ONOFF2
245 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
246 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
247 */
248 val = 0x50;
Jaehoon Chung40195a22017-01-09 14:47:50 +0900249 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, val);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000250
251 /* ONOFF3
252 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
253 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
254 */
255 val = 0x00;
Jaehoon Chung40195a22017-01-09 14:47:50 +0900256 ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF3, val);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000257
Jaehoon Chung40195a22017-01-09 14:47:50 +0900258 if (ret) {
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000259 puts("LCD pmic initialisation error!\n");
Jaehoon Chung40195a22017-01-09 14:47:50 +0900260 return -EINVAL;
261 }
262
263 return 0;
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000264}
265
Ajay Kumar41022a12013-02-21 23:52:57 +0000266void exynos_cfg_lcd_gpio(void)
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000267{
268 unsigned int i, f3_end = 4;
269
270 for (i = 0; i < 8; i++) {
271 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530272 gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
273 gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
274 gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000275 /* pull-up/down disable */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530276 gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
277 gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
278 gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000279
280 /* drive strength to max (24bit) */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530281 gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
282 gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
283 gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
284 gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
285 gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
286 gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000287 }
288
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530289 for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000290 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530291 gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000292 /* pull-up/down disable */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530293 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000294 /* drive strength to max (24bit) */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530295 gpio_set_drv(i, S5P_GPIO_DRV_4X);
296 gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000297 }
298
299 /* gpio pad configuration for LCD reset. */
Simon Glass4f83d3d2014-10-20 19:48:39 -0600300 gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530301 gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000302}
303
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100304int mipi_power(void)
305{
306 return 0;
307}
308
Ajay Kumar41022a12013-02-21 23:52:57 +0000309void exynos_reset_lcd(void)
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000310{
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530311 gpio_set_value(EXYNOS4_GPIO_Y45, 1);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000312 udelay(10000);
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530313 gpio_set_value(EXYNOS4_GPIO_Y45, 0);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000314 udelay(10000);
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530315 gpio_set_value(EXYNOS4_GPIO_Y45, 1);
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000316 udelay(100);
317}
318
Ajay Kumar41022a12013-02-21 23:52:57 +0000319void exynos_lcd_power_on(void)
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000320{
Jaehoon Chung40195a22017-01-09 14:47:50 +0900321 struct udevice *dev;
322 int ret;
323 u8 reg;
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000324
Jaehoon Chung40195a22017-01-09 14:47:50 +0900325 ret = pmic_get("max8998-pmic", &dev);
326 if (ret) {
327 puts("Failed to get MAX8998!\n");
Minkyu Kang538f26b2012-12-10 22:43:57 +0900328 return;
Jaehoon Chung40195a22017-01-09 14:47:50 +0900329 }
Minkyu Kang538f26b2012-12-10 22:43:57 +0900330
Jaehoon Chung40195a22017-01-09 14:47:50 +0900331 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
332 reg |= MAX8998_LDO17;
333 ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
334 if (ret) {
335 puts("MAX8998 LDO setting error\n");
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000336 return;
Jaehoon Chung40195a22017-01-09 14:47:50 +0900337 }
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000338
Jaehoon Chung40195a22017-01-09 14:47:50 +0900339 reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
340 reg |= MAX8998_LDO7;
341 ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
342 if (ret) {
343 puts("MAX8998 LDO setting error\n");
344 return;
345 }
Piotr Wilczek461c5e52012-10-19 05:34:07 +0000346}
347
Ajay Kumar41022a12013-02-21 23:52:57 +0000348void exynos_cfg_ldo(void)
349{
350 ld9040_cfg_ldo();
351}
352
353void exynos_enable_ldo(unsigned int onoff)
354{
355 ld9040_enable_ldo(onoff);
356}
357
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100358int exynos_init(void)
Piotr Wilczeke372b552012-10-19 05:34:03 +0000359{
Piotr Wilczeke372b552012-10-19 05:34:03 +0000360 gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100361
362 switch (get_hwrev()) {
363 case 0:
364 /*
365 * Set the low to enable LDO_EN
366 * But when you use the test board for eMMC booting
367 * you should set it HIGH since it removes the inverter
368 */
369 /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
Simon Glass4f83d3d2014-10-20 19:48:39 -0600370 gpio_request(EXYNOS4_GPIO_E36, "ldo_en");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530371 gpio_direction_output(EXYNOS4_GPIO_E36, 0);
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100372 break;
373 default:
374 /*
375 * Default reset state is High and there's no inverter
376 * But set it as HIGH to ensure
377 */
378 /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
Simon Glass4f83d3d2014-10-20 19:48:39 -0600379 gpio_request(EXYNOS4_GPIO_E13, "massmemory_en");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530380 gpio_direction_output(EXYNOS4_GPIO_E13, 1);
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100381 break;
382 }
Piotr Wilczeke372b552012-10-19 05:34:03 +0000383
Piotr Wilczeke372b552012-10-19 05:34:03 +0000384 check_hw_revision();
385 printf("HW Revision:\t0x%x\n", board_rev);
386
387 return 0;
388}
Przemyslaw Marczak283a3202014-01-22 11:24:12 +0100389
Simon Glassb4a967e2016-02-21 21:08:54 -0700390#ifdef CONFIG_LCD
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100391void exynos_lcd_misc_init(vidinfo_t *vid)
Przemyslaw Marczak283a3202014-01-22 11:24:12 +0100392{
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100393#ifdef CONFIG_TIZEN
394 get_tizen_logo_info(vid);
Przemyslaw Marczak283a3202014-01-22 11:24:12 +0100395#endif
Piotr Wilczek0ada4ad2014-03-07 14:59:47 +0100396
397 /* for LD9040. */
398 vid->pclk_name = 1; /* MPLL */
399 vid->sclk_div = 1;
400
Simon Glass6a38e412017-08-03 12:22:09 -0600401 env_set("lcdinfo", "lcd=ld9040");
Przemyslaw Marczak283a3202014-01-22 11:24:12 +0100402}
Simon Glassb4a967e2016-02-21 21:08:54 -0700403#endif