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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05002/*
Kumar Gala365024c2011-01-31 15:51:20 -06003 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05004 */
5
6#include <common.h>
7#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06008#include <env.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060012#include <net.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050013#include <pci.h>
14#include <asm/processor.h>
15#include <asm/mmu.h>
Kumar Galaf81f89f2008-09-22 14:11:11 -050016#include <asm/cache.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050017#include <asm/immap_85xx.h>
Kumar Gala9bbd6432009-04-02 13:22:48 -050018#include <asm/fsl_pci.h>
York Sunf0626592013-09-30 09:22:09 -070019#include <fsl_ddr_sdram.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050020#include <asm/io.h>
Kumar Gala3d020382010-12-15 04:55:20 -060021#include <asm/fsl_serdes.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050022#include <miiphy.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090023#include <linux/libfdt.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050024#include <fdt_support.h>
Liu Yuc49bce42008-10-10 11:40:59 +080025#include <tsec.h>
Andy Fleming422effd2011-04-08 02:10:54 -050026#include <fsl_mdio.h>
Kumar Galad3b1b662009-08-08 10:42:30 -050027#include <netdev.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050028
Liu Yuc49bce42008-10-10 11:40:59 +080029#include "../common/sgmii_riser.h"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050030
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050031int checkboard (void)
32{
Kumar Galae21db032009-07-14 22:42:01 -050033 u8 vboot;
34 u8 *pixis_base = (u8 *)PIXIS_BASE;
35
Timur Tabi56953ee2012-03-15 11:42:27 +000036 printf("Board: MPC8572DS Sys ID: 0x%02x, "
Kumar Galae21db032009-07-14 22:42:01 -050037 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
38 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
39 in_8(pixis_base + PIXIS_PVER));
40
41 vboot = in_8(pixis_base + PIXIS_VBOOT);
42 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
43 case PIXIS_VBOOT_LBMAP_NOR0:
44 puts ("vBank: 0\n");
45 break;
46 case PIXIS_VBOOT_LBMAP_PJET:
47 puts ("Promjet\n");
48 break;
49 case PIXIS_VBOOT_LBMAP_NAND:
50 puts ("NAND\n");
51 break;
52 case PIXIS_VBOOT_LBMAP_NOR1:
53 puts ("vBank: 1\n");
54 break;
55 }
56
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050057 return 0;
58}
59
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050060
61#if !defined(CONFIG_SPD_EEPROM)
62/*
63 * Fixed sdram init -- doesn't use serial presence detect.
64 */
65
66phys_size_t fixed_sdram (void)
67{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
York Suna21803d2013-11-18 10:29:32 -080069 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050070 uint d_init;
71
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
73 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
80 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
81 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
82 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
83 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
84 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050085
86#if defined (CONFIG_DDR_ECC)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
88 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
89 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050090#endif
91 asm("sync;isync");
92
93 udelay(500);
94
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050096
97#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
98 d_init = 1;
99 debug("DDR - 1st controller: memory initializing\n");
100 /*
101 * Poll until memory is initialized.
102 * 512 Meg at 400 might hit this 200 times or so.
103 */
104 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
105 udelay(1000);
106 }
107 debug("DDR: memory initialized\n\n");
108 asm("sync; isync");
109 udelay(500);
110#endif
111
112 return 512 * 1024 * 1024;
113}
114
115#endif
116
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500117#ifdef CONFIG_PCI
118void pci_init_board(void)
119{
Kumar Galad165dc52010-12-17 06:53:52 -0600120 struct pci_controller *hose;
Kumar Galafd19d1e2009-09-03 10:20:09 -0500121
Kumar Galad165dc52010-12-17 06:53:52 -0600122 fsl_pcie_init_board(0);
Kumar Galafd19d1e2009-09-03 10:20:09 -0500123
Kumar Galad165dc52010-12-17 06:53:52 -0600124 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500125
Kumar Galad165dc52010-12-17 06:53:52 -0600126 if (hose) {
127 u32 temp32;
128 u8 uli_busno = hose->first_busno + 2;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500129
Kumar Galafd19d1e2009-09-03 10:20:09 -0500130 /*
131 * Activate ULI1575 legacy chip by performing a fake
132 * memory access. Needed to make ULI RTC work.
133 * Device 1d has the first on-board memory BAR.
134 */
Kumar Galad165dc52010-12-17 06:53:52 -0600135 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
Kumar Galafd19d1e2009-09-03 10:20:09 -0500136 PCI_BASE_ADDRESS_1, &temp32);
Kumar Galad165dc52010-12-17 06:53:52 -0600137
Kumar Galafd19d1e2009-09-03 10:20:09 -0500138 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
Kumar Galad165dc52010-12-17 06:53:52 -0600139 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
Kumar Galafd19d1e2009-09-03 10:20:09 -0500140 temp32, 4, 0);
141 debug(" uli1572 read to %p\n", p);
142 in_be32(p);
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500143 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500144 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500145}
146#endif
147
148int board_early_init_r(void)
149{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -0700151 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500152
153 /*
154 * Remap Boot flash + PROMJET region to caching-inhibited
155 * so that flash can be erased properly.
156 */
157
Kumar Galaf81f89f2008-09-22 14:11:11 -0500158 /* Flush d-cache and invalidate i-cache of any FLASH data */
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100159 flush_dcache();
160 invalidate_icache();
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500161
York Sun220c3462014-06-24 21:16:20 -0700162 if (flash_esel == -1) {
163 /* very unlikely unless something is messed up */
164 puts("Error: Could not find TLB for FLASH BASE\n");
165 flash_esel = 2; /* give our best effort to continue */
166 } else {
167 /* invalidate existing TLB entry for flash + promjet */
168 disable_tlb(flash_esel);
169 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500170
Kumar Gala4be8b572008-12-02 14:19:34 -0600171 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500172 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
173 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
174
175 return 0;
176}
177
Liu Yuc49bce42008-10-10 11:40:59 +0800178int board_eth_init(bd_t *bis)
179{
Bin Meng28cedb22016-01-11 22:41:14 -0800180#ifdef CONFIG_TSEC_ENET
Andy Fleming422effd2011-04-08 02:10:54 -0500181 struct fsl_pq_mdio_info mdio_info;
Liu Yuc49bce42008-10-10 11:40:59 +0800182 struct tsec_info_struct tsec_info[4];
Liu Yuc49bce42008-10-10 11:40:59 +0800183 int num = 0;
184
185#ifdef CONFIG_TSEC1
186 SET_STD_TSEC_INFO(tsec_info[num], 1);
Kumar Galae6dc4842010-12-16 14:28:06 -0600187 if (is_serdes_configured(SGMII_TSEC1)) {
188 puts("eTSEC1 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800189 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600190 }
Liu Yuc49bce42008-10-10 11:40:59 +0800191 num++;
192#endif
193#ifdef CONFIG_TSEC2
194 SET_STD_TSEC_INFO(tsec_info[num], 2);
Kumar Galae6dc4842010-12-16 14:28:06 -0600195 if (is_serdes_configured(SGMII_TSEC2)) {
196 puts("eTSEC2 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800197 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600198 }
Liu Yuc49bce42008-10-10 11:40:59 +0800199 num++;
200#endif
201#ifdef CONFIG_TSEC3
202 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Galae6dc4842010-12-16 14:28:06 -0600203 if (is_serdes_configured(SGMII_TSEC3)) {
204 puts("eTSEC3 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800205 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600206 }
Liu Yuc49bce42008-10-10 11:40:59 +0800207 num++;
208#endif
209#ifdef CONFIG_TSEC4
210 SET_STD_TSEC_INFO(tsec_info[num], 4);
Kumar Galae6dc4842010-12-16 14:28:06 -0600211 if (is_serdes_configured(SGMII_TSEC4)) {
212 puts("eTSEC4 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800213 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600214 }
Liu Yuc49bce42008-10-10 11:40:59 +0800215 num++;
216#endif
217
218 if (!num) {
219 printf("No TSECs initialized\n");
220
221 return 0;
222 }
223
Andy Flemingacaccae2008-12-05 20:10:22 -0600224#ifdef CONFIG_FSL_SGMII_RISER
Liu Yuc49bce42008-10-10 11:40:59 +0800225 fsl_sgmii_riser_init(tsec_info, num);
Andy Flemingacaccae2008-12-05 20:10:22 -0600226#endif
Liu Yuc49bce42008-10-10 11:40:59 +0800227
Andy Fleming422effd2011-04-08 02:10:54 -0500228 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
229 mdio_info.name = DEFAULT_MII_NAME;
230 fsl_pq_mdio_init(bis, &mdio_info);
231
Liu Yuc49bce42008-10-10 11:40:59 +0800232 tsec_eth_init(bis, tsec_info, num);
Bin Meng28cedb22016-01-11 22:41:14 -0800233#endif
Liu Yuc49bce42008-10-10 11:40:59 +0800234
Kumar Galad3b1b662009-08-08 10:42:30 -0500235 return pci_eth_init(bis);
Liu Yuc49bce42008-10-10 11:40:59 +0800236}
Liu Yuc49bce42008-10-10 11:40:59 +0800237
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500238#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glass2aec3cc2014-10-23 18:58:47 -0600239int ft_board_setup(void *blob, bd_t *bd)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500240{
Kumar Galaf281c5c2009-02-09 22:03:04 -0600241 phys_addr_t base;
242 phys_size_t size;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500243
244 ft_cpu_setup(blob, bd);
245
Simon Glassda1a1342017-08-03 12:22:15 -0600246 base = env_get_bootm_low();
247 size = env_get_bootm_size();
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500248
249 fdt_fixup_memory(blob, (u64)base, (u64)size);
250
Kumar Galad0f27d32010-07-08 22:37:44 -0500251 FT_FSL_PCI_SETUP;
252
Andy Flemingacaccae2008-12-05 20:10:22 -0600253#ifdef CONFIG_FSL_SGMII_RISER
254 fsl_sgmii_riser_fdt_fixup(blob);
255#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600256
257 return 0;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500258}
259#endif