Michal Simek | 0fd9f36 | 2022-02-07 10:27:37 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2021, Xilinx. Inc. |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
Michal Simek | f0a6a32 | 2022-03-01 09:10:59 +0100 | [diff] [blame] | 8 | #include <dm/device_compat.h> |
Michal Simek | 0fd9f36 | 2022-02-07 10:27:37 +0100 | [diff] [blame] | 9 | #include <log.h> |
| 10 | #include <malloc.h> |
| 11 | #include <misc.h> |
| 12 | #include <power-domain-uclass.h> |
| 13 | #include <linux/bitops.h> |
| 14 | |
| 15 | #include <zynqmp_firmware.h> |
| 16 | |
Michal Simek | 0fd9f36 | 2022-02-07 10:27:37 +0100 | [diff] [blame] | 17 | static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
| 18 | const u32 qos, const enum zynqmp_pm_request_ack ack) |
| 19 | { |
| 20 | return xilinx_pm_request(PM_REQUEST_NODE, node, capabilities, |
| 21 | qos, ack, NULL); |
| 22 | } |
| 23 | |
| 24 | static int zynqmp_power_domain_request(struct power_domain *power_domain) |
| 25 | { |
Michal Simek | f0a6a32 | 2022-03-01 09:10:59 +0100 | [diff] [blame] | 26 | dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id); |
Michal Simek | 0fd9f36 | 2022-02-07 10:27:37 +0100 | [diff] [blame] | 27 | |
Michal Simek | f0a6a32 | 2022-03-01 09:10:59 +0100 | [diff] [blame] | 28 | return zynqmp_pmufw_node(power_domain->id); |
Michal Simek | 0fd9f36 | 2022-02-07 10:27:37 +0100 | [diff] [blame] | 29 | } |
| 30 | |
| 31 | static int zynqmp_power_domain_free(struct power_domain *power_domain) |
| 32 | { |
| 33 | /* nop now */ |
| 34 | return 0; |
| 35 | } |
| 36 | |
| 37 | static int zynqmp_power_domain_on(struct power_domain *power_domain) |
| 38 | { |
Michal Simek | f0a6a32 | 2022-03-01 09:10:59 +0100 | [diff] [blame] | 39 | dev_dbg(power_domain->dev, "Domain ON for id: %ld\n", power_domain->id); |
| 40 | |
Michal Simek | 0fd9f36 | 2022-02-07 10:27:37 +0100 | [diff] [blame] | 41 | return zynqmp_pm_request_node(power_domain->id, |
| 42 | ZYNQMP_PM_CAPABILITY_ACCESS, |
| 43 | ZYNQMP_PM_MAX_QOS, |
| 44 | ZYNQMP_PM_REQUEST_ACK_BLOCKING); |
| 45 | } |
| 46 | |
| 47 | static int zynqmp_power_domain_off(struct power_domain *power_domain) |
| 48 | { |
| 49 | /* nop now */ |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | struct power_domain_ops zynqmp_power_domain_ops = { |
| 54 | .request = zynqmp_power_domain_request, |
| 55 | .rfree = zynqmp_power_domain_free, |
| 56 | .on = zynqmp_power_domain_on, |
| 57 | .off = zynqmp_power_domain_off, |
| 58 | }; |
| 59 | |
| 60 | static int zynqmp_power_domain_probe(struct udevice *dev) |
| 61 | { |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | U_BOOT_DRIVER(zynqmp_power_domain) = { |
| 66 | .name = "zynqmp_power_domain", |
| 67 | .id = UCLASS_POWER_DOMAIN, |
| 68 | .probe = zynqmp_power_domain_probe, |
| 69 | .ops = &zynqmp_power_domain_ops, |
| 70 | }; |