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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * Workaround for layout bug on prototype board
33 */
34#define PCU_E_WITH_SWAPPED_CS 1
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
42#define CONFIG_MPC860T 1
43#define CONFIG_PCU_E 1 /* ...on a PCU E board */
44
Peter Tyser5c506212009-09-16 22:03:07 -050045#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
Peter Tyserd3d9a502009-09-16 22:03:08 -050046#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
Peter Tyser5c506212009-09-16 22:03:07 -050047
wdenk0f8c9762002-08-19 11:57:05 +000048#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
49
50#define CONFIG_BAUDRATE 9600
51#if 0
52#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
53#else
54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
55#endif
56
57#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
58
59#undef CONFIG_BOOTARGS
60#define CONFIG_BOOTCOMMAND \
61 "bootp;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010062 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk0f8c9762002-08-19 11:57:05 +000064 "bootm"
65
66#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +000068
69#undef CONFIG_WATCHDOG /* watchdog disabled */
70
71#define CONFIG_STATUS_LED 1 /* Status LED enabled */
72
73#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
74
75#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
76
77#define CONFIG_SPI /* enable SPI driver */
78#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
79
80#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
82#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk0f8c9762002-08-19 11:57:05 +000083
84
85/* ----------------------------------------------------------------
86 * Offset to initial SPI buffers in DPRAM (used if the environment
87 * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
88 * use at an early stage. It is used between the two initialization
89 * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
90 * far enough from the start of the data area (as well as from the
91 * stack pointer).
92 * ---------------------------------------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
wdenk0f8c9762002-08-19 11:57:05 +000094
wdenk0f8c9762002-08-19 11:57:05 +000095
Jon Loeligeraa2d2c22007-07-04 22:33:17 -050096/*
97 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100#define CONFIG_CMD_BSP
101#define CONFIG_CMD_DATE
102#define CONFIG_CMD_DHCP
103#define CONFIG_CMD_EEPROM
104#define CONFIG_CMD_NFS
105#define CONFIG_CMD_SNTP
wdenk0f8c9762002-08-19 11:57:05 +0000106
wdenk0f8c9762002-08-19 11:57:05 +0000107
Jon Loeligerc6d535a2007-07-09 21:57:31 -0500108/*
109 * BOOTP options
110 */
111#define CONFIG_BOOTP_SUBNETMASK
112#define CONFIG_BOOTP_HOSTNAME
113#define CONFIG_BOOTP_BOOTPATH
114#define CONFIG_BOOTP_BOOTFILESIZE
115
wdenk0f8c9762002-08-19 11:57:05 +0000116
117/*
118 * Miscellaneous configurable options
119 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_LONGHELP /* undef to save memory */
121#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligeraa2d2c22007-07-04 22:33:17 -0500122#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000124#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000126#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000130
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
132#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenk0f8c9762002-08-19 11:57:05 +0000137
138/* Ethernet hardware configuration done using port pins */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */
wdenk0f8c9762002-08-19 11:57:05 +0000140#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
142#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
143#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
144#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
145#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
wdenk0f8c9762002-08-19 11:57:05 +0000146#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */
148#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
149#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */
150#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */
151#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */
wdenk0f8c9762002-08-19 11:57:05 +0000152#endif /* XXX */
153
154/* Ethernet settings:
155 * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
156 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_ETH_MDDIS_VALUE 0
158#define CONFIG_SYS_ETH_CFG1_VALUE 1
159#define CONFIG_SYS_ETH_CFG2_VALUE 1
160#define CONFIG_SYS_ETH_CFG3_VALUE 1
wdenk0f8c9762002-08-19 11:57:05 +0000161
162/* PUMA configuration */
163#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */
wdenk0f8c9762002-08-19 11:57:05 +0000165#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */
wdenk0f8c9762002-08-19 11:57:05 +0000167#endif /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
169#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
wdenk0f8c9762002-08-19 11:57:05 +0000170
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000172
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000174
175/*
176 * Low Level Configuration Settings
177 * (address mappings, register initial values, etc.)
178 * You should know what you are doing if you make changes here.
179 */
180/*-----------------------------------------------------------------------
181 * Internal Memory Mapped Register
182 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_IMMR 0xFE000000
wdenk0f8c9762002-08-19 11:57:05 +0000184
185/*-----------------------------------------------------------------------
186 * Definitions for initial stack pointer and data area (in DPRAM)
187 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
189#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
190#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
191#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
192#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000193
194/*-----------------------------------------------------------------------
195 * Address accessed to reset the board - must not be mapped/assigned
196 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
wdenk0f8c9762002-08-19 11:57:05 +0000198
199/*-----------------------------------------------------------------------
200 * Start addresses for the final memory configuration
201 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000203 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk0f8c9762002-08-19 11:57:05 +0000205/* this is an ugly hack needed because of the silly non-constant address map */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
wdenk0f8c9762002-08-19 11:57:05 +0000207
208#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000210#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000212#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
214#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000215
216/*
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization.
220 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000222/*-----------------------------------------------------------------------
223 * FLASH organization
224 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
226#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
229#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000230
231#if 0
232/* Start port with environment in flash; switch to SPI EEPROM later */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200233#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200234#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
235#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
236#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
wdenk0f8c9762002-08-19 11:57:05 +0000237#else
238/* Final version: environment in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200239#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_I2C_EEPROM_ADDR 0
241#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200242#define CONFIG_ENV_OFFSET 1024
243#define CONFIG_ENV_SIZE 1024
wdenk0f8c9762002-08-19 11:57:05 +0000244#endif
245
246/*-----------------------------------------------------------------------
247 * Cache Configuration
248 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
250#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Heiko Schocher734f0272009-03-12 07:37:15 +0100251#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
252 * running in RAM.
253 */
wdenk0f8c9762002-08-19 11:57:05 +0000254
255/*-----------------------------------------------------------------------
256 * SYPCR - System Protection Control 11-9
257 * SYPCR can only be written once after reset!
258 *-----------------------------------------------------------------------
259 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
260 */
261#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk0f8c9762002-08-19 11:57:05 +0000263 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
264#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000266#endif
267
268/*-----------------------------------------------------------------------
269 * SIUMCR - SIU Module Configuration 11-6
270 *-----------------------------------------------------------------------
271 * External Arbitration max. priority (7),
272 * Debug pins configuration '11',
273 * Asynchronous external master enable.
274 */
275/* => 0x70600200 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
wdenk0f8c9762002-08-19 11:57:05 +0000277
278/*-----------------------------------------------------------------------
279 * TBSCR - Time Base Status and Control 11-26
280 *-----------------------------------------------------------------------
281 * Clear Reference Interrupt Status, Timebase freezing enabled
282 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk0f8c9762002-08-19 11:57:05 +0000284
285/*-----------------------------------------------------------------------
286 * PISCR - Periodic Interrupt Status and Control 11-31
287 *-----------------------------------------------------------------------
288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk0f8c9762002-08-19 11:57:05 +0000291
292/*-----------------------------------------------------------------------
293 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
294 *-----------------------------------------------------------------------
295 * Reset PLL lock status sticky bit, timer expired status bit and timer
296 * interrupt status bit, set PLL multiplication factor !
297 */
298/* 0x00004080 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
300#define CONFIG_SYS_PLPRCR \
301 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
wdenk0f8c9762002-08-19 11:57:05 +0000302 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
303 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
304 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
305 )
306
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000)
wdenk0f8c9762002-08-19 11:57:05 +0000308
309/*-----------------------------------------------------------------------
310 * SCCR - System Clock and reset Control Register 15-27
311 *-----------------------------------------------------------------------
312 * Set clock output, timebase and RTC source and divider,
313 * power management and some other internal clocks
314 *
315 * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
316 */
317#define SCCR_MASK SCCR_EBDF11
318/* 0x01800000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200319#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
wdenk0f8c9762002-08-19 11:57:05 +0000320 SCCR_RTDIV | SCCR_RTSEL | \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200321 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
wdenk0f8c9762002-08-19 11:57:05 +0000322 SCCR_EBDF00 | SCCR_DFSYNC00 | \
323 SCCR_DFBRG00 | SCCR_DFNL000 | \
324 SCCR_DFNH000 | SCCR_DFLCD100 | \
325 SCCR_DFALCD01)
326
327/*-----------------------------------------------------------------------
328 * RTCSC - Real-Time Clock Status and Control Register 11-27
329 *-----------------------------------------------------------------------
330 *
331 * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
332 *
333 * Don't expect the "date" command to work without a 32kHz clock input!
334 */
335/* 0x00C3 => 0x0003 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200336#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk0f8c9762002-08-19 11:57:05 +0000337
338
339/*-----------------------------------------------------------------------
340 * RCCR - RISC Controller Configuration Register 19-4
341 *-----------------------------------------------------------------------
342 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_RCCR 0x0000
wdenk0f8c9762002-08-19 11:57:05 +0000344
345/*-----------------------------------------------------------------------
346 * RMDS - RISC Microcode Development Support Control Register
347 *-----------------------------------------------------------------------
348 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#define CONFIG_SYS_RMDS 0
wdenk0f8c9762002-08-19 11:57:05 +0000350
351/*-----------------------------------------------------------------------
352 *
353 * Interrupt Levels
354 *-----------------------------------------------------------------------
355 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
wdenk0f8c9762002-08-19 11:57:05 +0000357
358/*-----------------------------------------------------------------------
359 *
360 *-----------------------------------------------------------------------
361 *
362 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200363#define CONFIG_SYS_DER 0
wdenk0f8c9762002-08-19 11:57:05 +0000364
365/*
366 * Init Memory Controller:
367 *
368 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
369 */
370
371#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
372#if PCU_E_WITH_SWAPPED_CS /* XXX */
373#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
374#else /* XXX */
375#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
376#endif /* XXX */
377
378/*
379 * used to re-map FLASH: restrict access enough but not too much to
380 * meddle with FLASH accesses
381 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200382#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
383#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenk0f8c9762002-08-19 11:57:05 +0000384
385/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200386#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
wdenk0f8c9762002-08-19 11:57:05 +0000387
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200388#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
389 CONFIG_SYS_OR_TIMING_FLASH)
390#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
391 CONFIG_SYS_OR_TIMING_FLASH)
wdenk0f8c9762002-08-19 11:57:05 +0000392/* 16 bit, bank valid */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200393#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000394
395#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200396#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP
397#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM
398#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000399#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200400#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
401#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
402#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000403#endif /* XXX */
404
405/*
406 * BR2/OR2: SDRAM
407 *
408 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
409 */
410#if PCU_E_WITH_SWAPPED_CS /* XXX */
411#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
412#else /* XXX */
413#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
414#endif /* XXX */
415#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
416#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
417
418#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
419
420#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200421#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
422#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000423#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200424#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
425#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000426#endif /* XXX */
427
428/*
429 * BR3/OR3: CAN Controller
430 * BR3: 0x10000401 OR3: 0xffff818a
431 */
432#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
433#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
434#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
435
436#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200437#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
438#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
wdenk0f8c9762002-08-19 11:57:05 +0000439#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200440#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
441#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
wdenk0f8c9762002-08-19 11:57:05 +0000442#endif /* XXX */
443
444/*
445 * BR4/OR4: PUMA Config
446 *
447 * Memory controller will be used in 2 modes:
448 *
449 * - "read" mode:
450 * BR4: 0x10100801 OR4: 0xffff8530
451 * - "load" mode (chip select on UPM B):
452 * BR4: 0x101008c1 OR4: 0xffff8630
453 *
454 * Default initialization is in "read" mode
455 */
456#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
457#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
458#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
459#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
460
461#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
462 BR_PS_16 | BR_MS_UPMB | BR_V)
463#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
464
465#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
466#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
467
468#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200469#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ
470#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ
wdenk0f8c9762002-08-19 11:57:05 +0000471#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200472#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
473#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
wdenk0f8c9762002-08-19 11:57:05 +0000474#endif /* XXX */
475
476/*
477 * BR5/OR5: PUMA: SMA Bus 8 Bit
478 * BR5: 0x10200401 OR5: 0xffe0010a
479 */
480#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
481#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
482#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
483
484#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200485#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
486#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000487#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200488#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
489#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000490#endif /* XXX */
491
492/*
493 * BR6/OR6: PUMA: SMA Bus 16 Bit
494 * BR6: 0x10600801 OR6: 0xffe0010a
495 */
496#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
497#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
498#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
499
500#if PCU_E_WITH_SWAPPED_CS /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200501#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
502#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000503#else /* XXX */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200504#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
505#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000506#endif /* XXX */
507
508/*
509 * BR7/OR7: PUMA: external Flash
510 * BR7: 0x10a00801 OR7: 0xfe00010a
511 */
512#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
513#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
514#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
515
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200516#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
517#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000518
519/*
520 * Memory Periodic Timer Prescaler
521 */
522
523/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200524#define CONFIG_SYS_MPTPR 0x0200
wdenk0f8c9762002-08-19 11:57:05 +0000525
526/*
527 * MAMR settings for SDRAM
528 * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
529 * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
530 * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
531 */
532/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200533#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */
wdenk0f8c9762002-08-19 11:57:05 +0000534
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200535#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
wdenk2bb11052003-07-17 23:16:40 +0000536 MAMR_AMA_TYPE_1 | \
537 MAMR_G0CLA_A10 | \
538 MAMR_RLFA_1X | \
539 MAMR_WLFA_1X | \
540 MAMR_TLFA_8X )
wdenk0f8c9762002-08-19 11:57:05 +0000541
542/*
543 * Internal Definitions
544 *
545 * Boot Flags
546 */
547#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
548#define BOOTFLAG_WARM 0x02 /* Software reboot */
549
550#endif /* __CONFIG_H */