blob: 46e3a6ce38c483056cfb7710fdfbd25050bf4c24 [file] [log] [blame]
wdenk9b7f3842003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk9b7f3842003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk9b7f3842003-10-09 20:09:04 +000015#define CONFIG_DBAU1X00 1
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090016#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk9b7f3842003-10-09 20:09:04 +000017
Daniel Schwierzeck2bc7eeb2014-11-15 23:30:01 +010018#define CONFIG_DISPLAY_BOARDINFO
19
wdenk4ea537d2003-12-07 18:32:37 +000020#ifdef CONFIG_DBAU1000
wdenk9b7f3842003-10-09 20:09:04 +000021/* Also known as Merlot */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090022#define CONFIG_SOC_AU1000 1
wdenk4ea537d2003-12-07 18:32:37 +000023#else
24#ifdef CONFIG_DBAU1100
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090025#define CONFIG_SOC_AU1100 1
wdenk4ea537d2003-12-07 18:32:37 +000026#else
27#ifdef CONFIG_DBAU1500
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090028#define CONFIG_SOC_AU1500 1
wdenk1ebf41e2004-01-02 14:00:00 +000029#else
wdenk96c7a8c2005-01-09 22:28:56 +000030#ifdef CONFIG_DBAU1550
31/* Cabernet */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090032#define CONFIG_SOC_AU1550 1
wdenk96c7a8c2005-01-09 22:28:56 +000033#else
wdenk4ea537d2003-12-07 18:32:37 +000034#error "No valid board set"
35#endif
36#endif
37#endif
wdenk96c7a8c2005-01-09 22:28:56 +000038#endif
wdenk9b7f3842003-10-09 20:09:04 +000039
wdenk9b7f3842003-10-09 20:09:04 +000040#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
41
42#define CONFIG_BAUDRATE 115200
43
44/* valid baudrates */
wdenk9b7f3842003-10-09 20:09:04 +000045
46#define CONFIG_TIMESTAMP /* Print image info with timestamp */
47#undef CONFIG_BOOTARGS
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010050 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
wdenk9b7f3842003-10-09 20:09:04 +000052 "panic=1\0" \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010054 "load=tftp 80500000 ${u-boot}\0" \
wdenk9b7f3842003-10-09 20:09:04 +000055 ""
wdenk96c7a8c2005-01-09 22:28:56 +000056
57#ifdef CONFIG_DBAU1550
58/* Boot from flash by default, revert to bootp */
59#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000060#else /* CONFIG_DBAU1550 */
Heiko Schocher65d4f8b2006-04-11 14:53:29 +020061#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000062#endif /* CONFIG_DBAU1550 */
63
Jon Loeligerb15a23b2007-07-04 22:32:03 -050064
65/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
74/*
Jon Loeligerb15a23b2007-07-04 22:32:03 -050075 * Command line configuration.
76 */
Jon Loeligerb15a23b2007-07-04 22:32:03 -050077#undef CONFIG_CMD_BEDBUG
78#undef CONFIG_CMD_ELF
Jon Loeligerb15a23b2007-07-04 22:32:03 -050079#undef CONFIG_CMD_FAT
Jon Loeligerb15a23b2007-07-04 22:32:03 -050080#undef CONFIG_CMD_MII
Jon Loeligerb15a23b2007-07-04 22:32:03 -050081
82#ifdef CONFIG_DBAU1550
83
Jon Loeligerb15a23b2007-07-04 22:32:03 -050084#undef CONFIG_CMD_I2C
85#undef CONFIG_CMD_IDE
Jon Loeligerb15a23b2007-07-04 22:32:03 -050086#undef CONFIG_CMD_PCMCIA
87
88#else
89
90#define CONFIG_CMD_IDE
91#define CONFIG_CMD_DHCP
92
Jon Loeligerb15a23b2007-07-04 22:32:03 -050093#endif
94
wdenk9b7f3842003-10-09 20:09:04 +000095
96/*
97 * Miscellaneous configurable options
98 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk96c7a8c2005-01-09 22:28:56 +0000100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
103#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk9b7f3842003-10-09 20:09:04 +0000104
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000108
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_SYS_MHZ 396
wdenk96c7a8c2005-01-09 22:28:56 +0000110
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#if (CONFIG_SYS_MHZ % 12) != 0
wdenk96c7a8c2005-01-09 22:28:56 +0000112#error "Invalid CPU frequency - must be multiple of 12!"
113#endif
114
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900116
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk9b7f3842003-10-09 20:09:04 +0000118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk9b7f3842003-10-09 20:09:04 +0000120
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_MEMTEST_START 0x80100000
122#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk9b7f3842003-10-09 20:09:04 +0000123
124/*-----------------------------------------------------------------------
125 * FLASH and environment organization
126 */
wdenk96c7a8c2005-01-09 22:28:56 +0000127#ifdef CONFIG_DBAU1550
128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
130#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenk96c7a8c2005-01-09 22:28:56 +0000131
132#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
133#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
134
wdenk96c7a8c2005-01-09 22:28:56 +0000135#else /* CONFIG_DBAU1550 */
136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
138#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk9b7f3842003-10-09 20:09:04 +0000139
140#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
141#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
142
wdenk96c7a8c2005-01-09 22:28:56 +0000143#endif /* CONFIG_DBAU1550 */
144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocher65d4f8b2006-04-11 14:53:29 +0200146
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200148#define CONFIG_FLASH_CFI_DRIVER 1
wdenk96c7a8c2005-01-09 22:28:56 +0000149
wdenk9b7f3842003-10-09 20:09:04 +0000150/* The following #defines are needed to get flash environment right */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk9b7f3842003-10-09 20:09:04 +0000153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk9b7f3842003-10-09 20:09:04 +0000155
156/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk9b7f3842003-10-09 20:09:04 +0000158
159/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
161#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk9b7f3842003-10-09 20:09:04 +0000162
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200163#define CONFIG_ENV_IS_NOWHERE 1
wdenk9b7f3842003-10-09 20:09:04 +0000164
165/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200166#define CONFIG_ENV_ADDR 0xB0030000
167#define CONFIG_ENV_SIZE 0x10000
wdenk9b7f3842003-10-09 20:09:04 +0000168
169#define CONFIG_FLASH_16BIT
170
171#define CONFIG_NR_DRAM_BANKS 2
172
wdenk9b7f3842003-10-09 20:09:04 +0000173
wdenk96c7a8c2005-01-09 22:28:56 +0000174#ifdef CONFIG_DBAU1550
175#define MEM_SIZE 192
176#else
177#define MEM_SIZE 64
178#endif
179
wdenk9b7f3842003-10-09 20:09:04 +0000180#define CONFIG_MEMSIZE_IN_BYTES
181
wdenk96c7a8c2005-01-09 22:28:56 +0000182#ifndef CONFIG_DBAU1550
wdenk9b7f3842003-10-09 20:09:04 +0000183/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
185#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk9b7f3842003-10-09 20:09:04 +0000186#define CONFIG_PCMCIA_SLOT_A
187
188#define CONFIG_ATAPI 1
189#define CONFIG_MAC_PARTITION 1
190
191/* We run CF in "true ide" mode or a harddrive via pcmcia */
192#define CONFIG_IDE_PCMCIA 1
193
194/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
196#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk9b7f3842003-10-09 20:09:04 +0000197
198#undef CONFIG_IDE_LED /* LED for ide not supported */
199#undef CONFIG_IDE_RESET /* reset for ide not supported */
200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9b7f3842003-10-09 20:09:04 +0000202
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk9b7f3842003-10-09 20:09:04 +0000204
wdenk1ebf41e2004-01-02 14:00:00 +0000205/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk9b7f3842003-10-09 20:09:04 +0000207
208/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk9b7f3842003-10-09 20:09:04 +0000210
211/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk96c7a8c2005-01-09 22:28:56 +0000213#endif /* CONFIG_DBAU1550 */
wdenk9b7f3842003-10-09 20:09:04 +0000214
215/*-----------------------------------------------------------------------
216 * Cache Configuration
217 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_DCACHE_SIZE 16384
219#define CONFIG_SYS_ICACHE_SIZE 16384
220#define CONFIG_SYS_CACHELINE_SIZE 32
wdenk9b7f3842003-10-09 20:09:04 +0000221
wdenk9b7f3842003-10-09 20:09:04 +0000222#endif /* __CONFIG_H */