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git01.mediatek.com / filogic / uboot / d9ffa5eda35c80c11066bbe6501000735eb2dffd / . / arch / arm / dts / fsl-imx8qxp-colibri.dts
blob: df992ac6396e4f16e4567378ebc27d15806006d5 [file] [log] [blame]
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6/dts-v1/;
7
8#include "fsl-imx8qxp.dtsi"
9#include "fsl-imx8qxp-colibri-u-boot.dtsi"
10
11/ {
Philippe Schenker336720f2020-08-28 21:08:05 +0300[diff] [blame]12 model = "Toradex Colibri iMX8X";
13 compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]14
15 chosen {
16 bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
17 stdout-path = &lpuart3;
18 };
19
20 reg_usbh_vbus: regulator-usbh-vbus {
21 compatible = "regulator-fixed";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_usbh1_reg>;
24 regulator-name = "usbh_vbus";
25 regulator-min-microvolt = <5000000>;
26 regulator-max-microvolt = <5000000>;
27 gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
28 };
29};
30
31&iomuxc {
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
34
Philippe Schenker336720f2020-08-28 21:08:05 +0300[diff] [blame]35 colibri-imx8x {
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]36 pinctrl_lpuart0: lpuart0grp {
37 fsl,pins = <
38 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
39 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
40 >;
41 };
42
43 pinctrl_lpuart3: lpuart3grp {
44 fsl,pins = <
45 SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
46 SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
47 >;
48 };
49
50 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
51 fsl,pins = <
52 SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
53 SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */
54 SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */
55 SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */
56 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */
57 SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */
58 >;
59 };
60
61 pinctrl_fec1: fec1grp {
62 fsl,pins = <
63 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */
64 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */
65 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
66 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
67 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
68 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
69 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
70 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
71 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
72 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
73 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
74 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061
75 >;
76 };
77
78 pinctrl_gpio_bl_on: gpio-bl-on {
79 fsl,pins = <
80 SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040
81 >;
82 };
83
84 pinctrl_hog0: hog0grp {
85 fsl,pins = <
86 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */
87 >;
88 };
89
90 pinctrl_hog1: hog1grp {
91 fsl,pins = <
92 SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */
93 SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */
94 SC_P_CSI_D07_CI_PI_D09 0x00000061
95 SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */
96 SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */
97 SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */
98 SC_P_CSI_D02_CI_PI_D04 0x00000061
99 SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */
100 SC_P_CSI_D06_CI_PI_D08 0x00000061
101 SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */
102 SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */
103 SC_P_CSI_D03_CI_PI_D05 0x00000061
104 SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */
105 SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */
106 SC_P_CSI_D00_CI_PI_D02 0x00000061
107 SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */
108 SC_P_CSI_D01_CI_PI_D03 0x00000061
109 SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */
110 SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */
111 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */
112 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */
113 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */
114 SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */
115 SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */
116 SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */
117 SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */
118 SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */
119 SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */
120 >;
121 };
122
123 pinctrl_hog2: hog2grp {
124 fsl,pins = <
125 SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */
126 SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */
127 SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */
128 SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */
129 >;
130 };
131
Oleksandr Suvorov70be7a22021-11-21 18:05:17 +0200[diff] [blame]132 /* On Module I2C */
133 pinctrl_i2c0: i2c0grp {
134 fsl,pins = <
135 SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
136 SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
137 >;
138 };
139
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]140 /* Off Module I2C */
141 pinctrl_i2c1: i2c1grp {
142 fsl,pins = <
143 SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
144 SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
145 >;
146 };
147
148 /*INT*/
149 pinctrl_usb3503a: usb3503a-grp {
150 fsl,pins = <
151 SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
152 >;
153 };
154
155 pinctrl_usbc_det: usbc-det {
156 fsl,pins = <
157 SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040
158 >;
159 };
160
161 pinctrl_usbh1_reg: usbh1-reg {
162 fsl,pins = <
163 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040
164 >;
165 };
166
167 pinctrl_usdhc1: usdhc1grp {
168 fsl,pins = <
169 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
170 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
171 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
172 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
173 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
174 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
175 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
176 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
177 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
178 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
179 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
180 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
181 >;
182 };
183
184 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
185 fsl,pins = <
186 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
187 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
188 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
189 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
190 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
191 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
192 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
193 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
194 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
195 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
196 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
197 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
198 >;
199 };
200
201 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
202 fsl,pins = <
203 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
204 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
205 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
206 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
207 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
208 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
209 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
210 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
211 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
212 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
213 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
214 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
215 >;
216 };
217
218 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
219 fsl,pins = <
220 SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021
221 >;
222 };
223
224 pinctrl_usdhc2: usdhc2grp {
225 fsl,pins = <
226 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
227 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
228 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
229 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
230 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
231 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
232 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
233 >;
234 };
235
236 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
237 fsl,pins = <
238 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
239 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
240 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
241 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
242 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
243 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
244 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
245 >;
246 };
247
248 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
249 fsl,pins = <
250 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
251 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
252 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
253 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
254 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
255 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
256 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
257 >;
258 };
259 };
260};
261
262&lpuart0 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_lpuart0>;
265 status = "okay";
266};
267
268&lpuart3 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
271 status = "okay";
272};
273
274&gpio0 {
275 status = "okay";
276};
277
278&gpio1 {
279 status = "okay";
280};
281
282&gpio3 {
283 status = "okay";
284};
285
286&gpio4 {
287 status = "okay";
288};
289
290&fec1 {
291 phy-handle = <&ethphy0>;
292 phy-mode = "rmii";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_fec1>;
295 status = "okay";
296
297 mdio {
298 #address-cells = <1>;
299 #size-cells = <0>;
300
301 ethphy0: ethernet-phy@2 {
302 compatible = "ethernet-phy-ieee802.3-c22";
303 max-speed = <100>;
304 reg = <2>;
305 };
306 };
307};
308
Oleksandr Suvorov70be7a22021-11-21 18:05:17 +0200[diff] [blame]309&i2c0 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 clock-frequency = <100000>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_i2c0>;
315 status = "okay";
316
317 /* GPIO expander */
318 gpio_expander_43: gpio-expander@43 {
319 compatible = "fcs,fxl6408";
320 gpio-controller;
321 #gpio-cells = <2>;
322 reg = <0x43>;
323 initial_io_dir = <0xff>;
324 initial_output = <0x05>;
325 };
326};
327
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]328&i2c1 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clock-frequency = <100000>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_i2c1>;
334 status = "okay";
335};
336
337&usdhc1 {
338 bus-width = <8>;
339 non-removable;
340 pinctrl-names = "default", "state_100mhz", "state_200mhz";
341 pinctrl-0 = <&pinctrl_usdhc1>;
342 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
343 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
344 status = "okay";
345};
346
347&usdhc2 {
348 bus-width = <4>;
349 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
350 pinctrl-names = "default", "state_100mhz", "state_200mhz";
351 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
352 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
353 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
354 status = "okay";
355};