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git01.mediatek.com / filogic / uboot / d97307de8719e162d253e4b1fbf5da5a55348864 / . / arch / arm / dts / fsl-ls1088a.dtsi
blob: f8f8654e151a403264c9fd48a571ca622e6d7fc5 [file] [log] [blame]
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]1/*
2 * NXP ls1088a SOC common device tree source
3 *
4 * Copyright 2017 NXP
5 *
Pankaj Bansal45254cf2018-01-18 09:43:33 +0530[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+ X11
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]7 */
8
9/ {
10 compatible = "fsl,ls1088a";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 memory@80000000 {
16 device_type = "memory";
17 reg = <0x00000000 0x80000000 0 0x80000000>;
18 /* DRAM space - 1, size : 2 GB DRAM */
19 };
20
21 gic: interrupt-controller@6000000 {
22 compatible = "arm,gic-v3";
23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
25 #interrupt-cells = <3>;
26 interrupt-controller;
27 interrupts = <1 9 0x4>;
28 };
29
30 timer {
31 compatible = "arm,armv8-timer";
32 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
33 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
34 <1 11 0x8>, /* Virtual PPI, active-low */
35 <1 10 0x8>; /* Hypervisor PPI, active-low */
36 };
37
38 serial0: serial@21c0500 {
39 device_type = "serial";
40 compatible = "fsl,ns16550", "ns16550a";
41 reg = <0x0 0x21c0500 0x0 0x100>;
42 clock-frequency = <0>; /* Updated by bootloader */
43 interrupts = <0 32 0x1>; /* edge triggered */
44 };
45
46 serial1: serial@21c0600 {
47 device_type = "serial";
48 compatible = "fsl,ns16550", "ns16550a";
49 reg = <0x0 0x21c0600 0x0 0x100>;
50 clock-frequency = <0>; /* Updated by bootloader */
51 interrupts = <0 32 0x1>; /* edge triggered */
52 };
53
54 fsl_mc: fsl-mc@80c000000 {
55 compatible = "fsl,qoriq-mc";
56 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
57 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
58 };
59
60 dspi: dspi@2100000 {
61 compatible = "fsl,vf610-dspi";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <0x0 0x2100000 0x0 0x10000>;
65 interrupts = <0 26 0x4>; /* Level high type */
66 num-cs = <6>;
67 };
68
69 qspi: quadspi@1550000 {
70 compatible = "fsl,vf610-qspi";
71 #address-cells = <1>;
72 #size-cells = <0>;
73 reg = <0x0 0x20c0000 0x0 0x10000>,
74 <0x0 0x20000000 0x0 0x10000000>;
75 reg-names = "QuadSPI", "QuadSPI-memory";
76 num-cs = <4>;
77 };
Hou Zhiqiang6ae9a8c2017-09-04 10:47:53 +0800[diff] [blame]78
Ran Wang9a43a6c2017-10-23 10:09:24 +0800[diff] [blame]79 usb0: usb3@3100000 {
80 compatible = "fsl,layerscape-dwc3";
81 reg = <0x0 0x3100000 0x0 0x10000>;
82 interrupts = <0 80 0x4>; /* Level high type */
83 dr_mode = "host";
84 };
85
86 usb1: usb3@3110000 {
87 compatible = "fsl,layerscape-dwc3";
88 reg = <0x0 0x3110000 0x0 0x10000>;
89 interrupts = <0 81 0x4>; /* Level high type */
90 dr_mode = "host";
91 };
92
Hou Zhiqiang6ae9a8c2017-09-04 10:47:53 +0800[diff] [blame]93 pcie@3400000 {
94 compatible = "fsl,ls-pcie", "snps,dw-pcie";
95 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
96 0x00 0x03480000 0x0 0x80000 /* lut registers */
97 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
98 0x20 0x00000000 0x0 0x20000>; /* configuration space */
99 reg-names = "dbi", "lut", "ctrl", "config";
100 #address-cells = <3>;
101 #size-cells = <2>;
102 device_type = "pci";
103 num-lanes = <4>;
104 bus-range = <0x0 0xff>;
105 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
106 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
107 };
108
109 pcie@3500000 {
110 compatible = "fsl,ls-pcie", "snps,dw-pcie";
111 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
112 0x00 0x03580000 0x0 0x80000 /* lut registers */
113 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
114 0x28 0x00000000 0x0 0x20000>; /* configuration space */
115 reg-names = "dbi", "lut", "ctrl", "config";
116 #address-cells = <3>;
117 #size-cells = <2>;
118 device_type = "pci";
119 num-lanes = <4>;
120 bus-range = <0x0 0xff>;
121 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
122 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
123 };
124
125 pcie@3600000 {
126 compatible = "fsl,ls-pcie", "snps,dw-pcie";
127 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
128 0x00 0x03680000 0x0 0x80000 /* lut registers */
129 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
130 0x30 0x00000000 0x0 0x20000>; /* configuration space */
131 reg-names = "dbi", "lut", "ctrl", "config";
132 #address-cells = <3>;
133 #size-cells = <2>;
134 device_type = "pci";
135 num-lanes = <8>;
136 bus-range = <0x0 0xff>;
137 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
138 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
139 };
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]140};