blob: b16f10d410ff6b19e3d7369faf149e4f8fd437d6 [file] [log] [blame]
Thierry Reding52d6c122012-06-04 20:02:30 +00001/dts-v1/;
2
Tom Warrene41e11b2013-02-21 12:31:28 +00003#include "tegra20-tamonten.dtsi"
Thierry Reding52d6c122012-06-04 20:02:30 +00004
5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier";
Thierry Redingd63438b2012-09-19 00:37:20 +00007 compatible = "ad,tec", "nvidia,tegra20";
Thierry Reding52d6c122012-06-04 20:02:30 +00008
Simon Glass0c24f372014-09-04 16:27:35 -06009 chosen {
10 stdout-path = &uartd;
11 };
12
Thierry Reding52d6c122012-06-04 20:02:30 +000013 aliases {
14 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +000015 sdhci0 = "/sdhci@c8000600";
Thierry Reding52d6c122012-06-04 20:02:30 +000016 };
17
18 memory {
19 reg = <0x00000000 0x20000000>;
20 };
21
Simon Glasse31a2a52016-01-30 16:37:52 -070022 host1x@50000000 {
Thierry Redingc9318632012-11-23 00:58:51 +000023 status = "okay";
24
25 dc@54200000 {
26 status = "okay";
27
28 rgb {
29 nvidia,panel = <&lcd_panel>;
30 status = "okay";
31 };
32 };
33 };
34
Thierry Reding52d6c122012-06-04 20:02:30 +000035 serial@70006300 {
36 clock-frequency = <216000000>;
37 };
38
39 i2c@7000c000 {
40 status = "disabled";
41 };
42
43 i2c@7000c400 {
44 status = "disabled";
45 };
46
47 i2c@7000c500 {
48 status = "disabled";
49 };
50
51 i2c@7000d000 {
52 status = "disabled";
53 };
54
Thierry Redingc9318632012-11-23 00:58:51 +000055 lcd_panel: panel {
56 clock = <33260000>;
57 xres = <800>;
58 yres = <480>;
59 left-margin = <120>;
60 right-margin = <120>;
61 hsync-len = <16>;
62 lower-margin = <15>;
63 upper-margin = <15>;
64 vsync-len = <15>;
65
66 nvidia,bits-per-pixel = <16>;
67 nvidia,pwm = <&pwm 0 500000>;
Simon Glass3112fd52015-01-05 20:05:41 -070068 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
69 GPIO_ACTIVE_HIGH>;
70 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
71 GPIO_ACTIVE_HIGH>;
72 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
73 GPIO_ACTIVE_HIGH>;
Thierry Redingc9318632012-11-23 00:58:51 +000074 nvidia,panel-timings = <0 0 0 0>;
75 };
Thierry Reding52d6c122012-06-04 20:02:30 +000076};