| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 2 | /* |
| Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 3 | * (C) Copyright 2010-2015 |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 4 | * NVIDIA Corporation <www.nvidia.com> |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _TEGRA_GP_PADCTRL_H_ |
| 8 | #define _TEGRA_GP_PADCTRL_H_ |
| 9 | |
| 10 | #define GP_HIDREV 0x804 |
| 11 | |
| 12 | /* bit fields definitions for APB_MISC_GP_HIDREV register */ |
| 13 | #define HIDREV_CHIPID_SHIFT 8 |
| 14 | #define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) |
| 15 | #define HIDREV_MAJORPREV_SHIFT 4 |
| 16 | #define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) |
| 17 | |
| 18 | /* CHIPID field returned from APB_MISC_GP_HIDREV register */ |
| 19 | #define CHIPID_TEGRA20 0x20 |
| 20 | #define CHIPID_TEGRA30 0x30 |
| Tom Warren | c47e717 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 21 | #define CHIPID_TEGRA114 0x35 |
| Tom Warren | b7ea6d1 | 2014-01-24 12:46:13 -0700 | [diff] [blame] | 22 | #define CHIPID_TEGRA124 0x40 |
| Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 23 | #define CHIPID_TEGRA210 0x21 |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 24 | |
| 25 | #endif /* _TEGRA_GP_PADCTRL_H_ */ |