| wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <mpc8xx.h> |
| 9 | #include <ppc_asm.tmpl> |
| 10 | #include <asm/cache.h> |
| 11 | |
| 12 | #define CACHE_CMD_ENABLE 0x02000000 |
| 13 | #define CACHE_CMD_DISABLE 0x04000000 |
| 14 | #define CACHE_CMD_LOAD_LOCK 0x06000000 |
| 15 | #define CACHE_CMD_UNLOCK_LINE 0x08000000 |
| 16 | #define CACHE_CMD_UNLOCK_ALL 0x0A000000 |
| 17 | #define CACHE_CMD_INVALIDATE 0x0C000000 |
| 18 | #define SPEED_PLPRCR_WAIT_5CYC 150 |
| 19 | #define _CACHE_ALIGN_SIZE 16 |
| 20 | |
| 21 | |
| 22 | .text |
| 23 | .align 2 |
| 24 | .globl plprcr_write_866 |
| 25 | |
| 26 | /* |
| 27 | * void plprcr_write_866 (long plprcr) |
| 28 | * Write PLPRCR, including workaround for device errata SIU4 and SIU9. |
| 29 | */ |
| 30 | |
| 31 | plprcr_write_866: |
| 32 | mfspr r10, LR /* save the Link Register value */ |
| 33 | |
| 34 | /* turn instruction cache on (no MMU required for instructions) |
| 35 | */ |
| 36 | lis r4, CACHE_CMD_ENABLE@h |
| 37 | ori r4, r4, CACHE_CMD_ENABLE@l |
| 38 | mtspr IC_CST, r4 |
| 39 | isync |
| 40 | |
| 41 | /* clear IC_CST error bits |
| 42 | */ |
| 43 | mfspr r4, IC_CST |
| 44 | |
| 45 | bl plprcr_here |
| 46 | |
| 47 | plprcr_here: |
| 48 | mflr r5 |
| 49 | |
| 50 | /* calculate relocation offset |
| 51 | */ |
| 52 | lis r4, plprcr_here@h |
| 53 | ori r4, r4, plprcr_here@l |
| 54 | sub r5, r5, r4 |
| 55 | |
| 56 | /* calculate first address of this function |
| 57 | */ |
| 58 | lis r6, plprcr_write_866@h |
| 59 | ori r6, r6, plprcr_write_866@l |
| 60 | add r6, r6, r5 |
| 61 | |
| 62 | /* calculate end address of this function |
| 63 | */ |
| 64 | lis r7, plprcr_end@h |
| 65 | ori r7, r7, plprcr_end@l |
| 66 | add r7, r7, r5 |
| 67 | |
| 68 | /* load and lock code addresses |
| 69 | */ |
| 70 | mr r5, r6 |
| 71 | |
| 72 | plprcr_loop: |
| 73 | mtspr IC_ADR, r5 |
| 74 | addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */ |
| 75 | |
| 76 | lis r4, CACHE_CMD_LOAD_LOCK@h |
| 77 | ori r4, r4, CACHE_CMD_LOAD_LOCK@l |
| 78 | mtspr IC_CST, r4 |
| 79 | isync |
| 80 | |
| 81 | cmpw r5, r7 |
| 82 | blt plprcr_loop |
| 83 | |
| 84 | /* IC_CST error bits not evaluated |
| 85 | */ |
| 86 | |
| 87 | /* switch PLPRCR |
| 88 | */ |
| 89 | mfspr r4, IMMR /* read IMMR */ |
| 90 | rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */ |
| 91 | |
| 92 | /* write sequence according to MPC866 Errata |
| 93 | */ |
| 94 | stw r3, PLPRCR(r4) |
| 95 | isync |
| 96 | |
| 97 | lis r3, SPEED_PLPRCR_WAIT_5CYC@h |
| 98 | ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l |
| 99 | |
| 100 | plprcr_wait: |
| 101 | cmpwi r3, 0 |
| 102 | beq plprcr_wait_end |
| 103 | nop |
| 104 | subi r3, r3, 1 |
| 105 | b plprcr_wait |
| 106 | |
| 107 | plprcr_wait_end: |
| 108 | |
| wdenk | 4b6e905 | 2004-02-06 21:48:22 +0000 | [diff] [blame] | 109 | /* unlock instruction cache but leave it enabled |
| wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 110 | */ |
| 111 | lis r4, CACHE_CMD_UNLOCK_ALL@h |
| 112 | ori r4, r4, CACHE_CMD_UNLOCK_ALL@l |
| 113 | mtspr IC_CST, r4 |
| 114 | isync |
| 115 | |
| wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 116 | mtspr LR, r10 /* restore original Link Register value */ |
| 117 | blr |
| 118 | |
| 119 | plprcr_end: |