| Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins |
| 3 | * |
| 4 | * Copyright 2009: Marvell Technology Group Ltd. |
| 5 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __KIRKWOOD_MPP_H |
| 10 | #define __KIRKWOOD_MPP_H |
| 11 | |
| 12 | #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ |
| 13 | /* MPP number */ ((_num) & 0xff) | \ |
| 14 | /* MPP select value */ (((_sel) & 0xf) << 8) | \ |
| 15 | /* may be input signal */ ((!!(_in)) << 12) | \ |
| 16 | /* may be output signal */ ((!!(_out)) << 13) | \ |
| 17 | /* available on F6180 */ ((!!(_F6180)) << 14) | \ |
| 18 | /* available on F6190 */ ((!!(_F6190)) << 15) | \ |
| 19 | /* available on F6192 */ ((!!(_F6192)) << 16) | \ |
| 20 | /* available on F6281 */ ((!!(_F6281)) << 17)) |
| 21 | |
| 22 | #define MPP_NUM(x) ((x) & 0xff) |
| 23 | #define MPP_SEL(x) (((x) >> 8) & 0xf) |
| 24 | |
| 25 | /* num sel i o 6180 6190 6192 6281 */ |
| 26 | |
| 27 | #define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) |
| 28 | #define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) |
| 29 | |
| 30 | #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) |
| 31 | #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) |
| 32 | #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) |
| 33 | #define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) |
| 34 | |
| 35 | #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 36 | #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 37 | #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 38 | |
| 39 | #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 40 | #define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 41 | #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 42 | |
| 43 | #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 44 | #define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 45 | #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 46 | |
| 47 | #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 48 | #define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 49 | #define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) |
| 50 | |
| 51 | #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 52 | #define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 53 | #define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) |
| 54 | #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) |
| 55 | #define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) |
| 56 | |
| 57 | #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 58 | #define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 59 | #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 60 | #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) |
| 61 | #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) |
| 62 | |
| 63 | #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) |
| 64 | #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 65 | #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) |
| 66 | |
| 67 | #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 68 | #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) |
| 69 | #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 70 | #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) |
| 71 | |
| Luka Perkov | 6c46604 | 2012-09-05 08:08:16 +0000 | [diff] [blame] | 72 | #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) |
| Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 73 | #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 74 | #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 75 | #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) |
| 76 | #define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) |
| 77 | #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) |
| 78 | #define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) |
| 79 | #define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) |
| 80 | |
| 81 | #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 82 | #define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 83 | #define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) |
| 84 | #define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) |
| 85 | #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) |
| 86 | #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) |
| 87 | #define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) |
| 88 | |
| 89 | #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 90 | #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 91 | #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) |
| 92 | #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) |
| 93 | #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) |
| 94 | |
| 95 | #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 96 | #define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) |
| 97 | #define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) |
| 98 | #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) |
| 99 | #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) |
| 100 | #define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) |
| 101 | #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) |
| 102 | |
| 103 | #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 104 | #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) |
| 105 | |
| 106 | #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 107 | #define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 108 | #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) |
| 109 | |
| 110 | #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 111 | #define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 112 | #define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) |
| 113 | #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 114 | #define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) |
| 115 | |
| 116 | #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 117 | #define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 118 | #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) |
| 119 | #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) |
| 120 | #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) |
| 121 | |
| 122 | #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 123 | #define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 124 | #define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) |
| 125 | #define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) |
| 126 | #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 127 | #define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) |
| 128 | |
| 129 | #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 130 | #define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 131 | #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) |
| 132 | |
| 133 | #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 134 | #define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 135 | |
| 136 | #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) |
| 137 | #define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) |
| 138 | |
| 139 | #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 140 | #define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 141 | #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 142 | #define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 143 | #define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) |
| 144 | #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) |
| 145 | |
| 146 | #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 147 | #define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 148 | #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 149 | #define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 150 | #define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 151 | #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) |
| 152 | |
| 153 | #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 154 | #define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 155 | #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 156 | #define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 157 | #define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 158 | #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) |
| 159 | |
| 160 | #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 161 | #define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 162 | #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) |
| 163 | #define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 164 | #define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 165 | #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) |
| 166 | |
| 167 | #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 168 | #define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 169 | #define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 170 | #define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 171 | #define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 172 | |
| 173 | #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 174 | #define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 175 | #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 176 | #define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 177 | #define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 178 | |
| 179 | #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 180 | #define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 181 | #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) |
| 182 | #define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 183 | #define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) |
| 184 | |
| 185 | #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 186 | #define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 187 | #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 188 | #define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 189 | #define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) |
| 190 | |
| 191 | #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 192 | #define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 193 | #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) |
| 194 | #define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 195 | #define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) |
| 196 | |
| 197 | #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 198 | #define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 199 | #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) |
| 200 | #define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 201 | |
| 202 | #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 203 | #define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 204 | #define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) |
| 205 | #define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 206 | |
| 207 | #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 208 | #define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 209 | #define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) |
| 210 | #define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 211 | |
| 212 | #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 213 | #define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) |
| 214 | #define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) |
| 215 | #define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 216 | |
| 217 | #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 218 | #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 219 | #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 220 | |
| 221 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) |
| 222 | #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 223 | #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 224 | |
| 225 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) |
| 226 | #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) |
| 227 | #define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) |
| 228 | #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) |
| 229 | #define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) |
| 230 | |
| 231 | #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 232 | #define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 233 | #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 234 | #define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) |
| 235 | |
| 236 | #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 237 | #define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 238 | #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 239 | #define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) |
| 240 | |
| 241 | #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 242 | #define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 243 | #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 244 | #define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) |
| 245 | |
| 246 | #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 247 | #define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 248 | #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 249 | #define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) |
| 250 | |
| 251 | #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 252 | #define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 253 | #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 254 | #define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) |
| 255 | |
| 256 | #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 257 | #define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 258 | #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) |
| 259 | #define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) |
| 260 | |
| 261 | #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 262 | #define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 263 | #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 264 | #define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) |
| 265 | |
| 266 | #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 267 | #define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 268 | #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) |
| 269 | #define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) |
| 270 | |
| 271 | #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) |
| 272 | #define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 273 | #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) |
| 274 | #define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) |
| 275 | |
| 276 | #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) |
| 277 | #define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 278 | #define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) |
| 279 | |
| 280 | #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) |
| 281 | #define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 282 | #define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) |
| 283 | |
| 284 | #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) |
| 285 | #define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 286 | #define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) |
| 287 | |
| 288 | #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) |
| 289 | #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) |
| Simon Kagstrom | 93d033b | 2009-06-30 23:03:31 +0200 | [diff] [blame] | 290 | #define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) |
| Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 291 | |
| 292 | #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) |
| 293 | #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) |
| 294 | #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) |
| 295 | #define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) |
| 296 | |
| 297 | #define MPP_MAX 49 |
| 298 | |
| Albert ARIBAUD | 4d42431 | 2012-11-26 11:27:36 +0000 | [diff] [blame] | 299 | void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); |
| Prafulla Wadaskar | a09bbe5 | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 300 | |
| 301 | #endif |