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Tom Rix330a90a2009-06-28 12:52:29 -05001/*
2 * Copyright (c) 2009 Wind River Systems, Inc.
3 * Tom Rix <Tom.Rix at windriver.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
Tom Rix0f2a8042009-06-28 12:52:30 -050020 * twl4030_power_reset_init is derived from code on omapzoom,
21 * git://git.omapzoom.com/repo/u-boot.git
Tom Rix330a90a2009-06-28 12:52:29 -050022 *
23 * Copyright (C) 2007-2009 Texas Instruments, Inc.
Tom Rix0f2a8042009-06-28 12:52:30 -050024 *
25 * twl4030_power_init is from cpu/omap3/common.c, power_init_r
26 *
27 * (C) Copyright 2004-2008
28 * Texas Instruments, <www.ti.com>
29 *
30 * Author :
31 * Sunil Kumar <sunilsaini05 at gmail.com>
32 * Shashi Ranjan <shashiranjanmca05 at gmail.com>
33 *
34 * Derived from Beagle Board and 3430 SDP code by
35 * Richard Woodruff <r-woodruff2 at ti.com>
36 * Syed Mohammed Khasim <khasim at ti.com>
37 *
Tom Rix330a90a2009-06-28 12:52:29 -050038 */
39
40#include <twl4030.h>
41
42/*
43 * Power Reset
44 */
45void twl4030_power_reset_init(void)
46{
47 u8 val = 0;
Nishanth Menon5d9d6f72013-03-26 05:20:50 +000048 if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
49 TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) {
Tom Rix330a90a2009-06-28 12:52:29 -050050 printf("Error:TWL4030: failed to read the power register\n");
51 printf("Could not initialize hardware reset\n");
52 } else {
53 val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
Nishanth Menond26a1062013-03-26 05:20:49 +000054 if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
55 TWL4030_PM_MASTER_P1_SW_EVENTS, val)) {
Tom Rix330a90a2009-06-28 12:52:29 -050056 printf("Error:TWL4030: failed to write the power register\n");
57 printf("Could not initialize hardware reset\n");
58 }
59 }
60}
61
Tom Rix0f2a8042009-06-28 12:52:30 -050062/*
Steve Sakomana18fc3f2010-08-10 12:58:39 -070063 * Set Device Group and Voltage
Tom Rix0f2a8042009-06-28 12:52:30 -050064 */
Steve Sakomana18fc3f2010-08-10 12:58:39 -070065void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
66 u8 dev_grp, u8 dev_grp_sel)
67{
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +000068 int ret;
Steve Sakomana18fc3f2010-08-10 12:58:39 -070069
70 /* Select the Voltage */
Nishanth Menond26a1062013-03-26 05:20:49 +000071 ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg,
72 vsel_val);
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +000073 if (ret != 0) {
Peter Meerwaldcc2884a2012-11-19 23:13:04 +000074 printf("Could not write vsel to reg %02x (%d)\n",
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +000075 vsel_reg, ret);
76 return;
77 }
78
79 /* Select the Device Group (enable the supply if dev_grp_sel != 0) */
Nishanth Menond26a1062013-03-26 05:20:49 +000080 ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp,
81 dev_grp_sel);
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +000082 if (ret != 0)
Peter Meerwaldcc2884a2012-11-19 23:13:04 +000083 printf("Could not write grp_sel to reg %02x (%d)\n",
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +000084 dev_grp, ret);
Steve Sakomana18fc3f2010-08-10 12:58:39 -070085}
Tom Rix0f2a8042009-06-28 12:52:30 -050086
87void twl4030_power_init(void)
88{
Tom Rix0f2a8042009-06-28 12:52:30 -050089 /* set VAUX3 to 2.8V */
Steve Sakomana18fc3f2010-08-10 12:58:39 -070090 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
91 TWL4030_PM_RECEIVER_VAUX3_VSEL_28,
92 TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
93 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix0f2a8042009-06-28 12:52:30 -050094
95 /* set VPLL2 to 1.8V */
Steve Sakomana18fc3f2010-08-10 12:58:39 -070096 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
97 TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
98 TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
99 TWL4030_PM_RECEIVER_DEV_GRP_ALL);
Tom Rix0f2a8042009-06-28 12:52:30 -0500100
101 /* set VDAC to 1.8V */
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700102 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
103 TWL4030_PM_RECEIVER_VDAC_VSEL_18,
104 TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
105 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix0f2a8042009-06-28 12:52:30 -0500106}
Tom Rix330a90a2009-06-28 12:52:29 -0500107
Tom Rix247e3c22009-06-28 12:52:31 -0500108void twl4030_power_mmc_init(void)
109{
Ash Charles3ce63782011-09-28 06:47:16 +0000110 /* Set VMMC1 to 3.15 Volts */
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700111 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
Ash Charles3ce63782011-09-28 06:47:16 +0000112 TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700113 TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
114 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix247e3c22009-06-28 12:52:31 -0500115}