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git01.mediatek.com / filogic / uboot / 1234ce736c362fe962aba9f3a07ba4601bf69e4b / . / board / micronas / vct / dcgu.h
blob: ca129c0129cf8556612d6e55b2e2b20877c777d6 [file] [log] [blame]
Stefan Roese9182d2f2009-01-21 17:24:39 +0100[diff] [blame]1/*
2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
4 * Copyright (C) 2006 Micronas GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef _DCGU_H
23#define _DCGU_H
24
25enum dcgu_switch {
26 DCGU_SWITCH_OFF, /* Switch off */
27 DCGU_SWITCH_ON /* Switch on */
28};
29
30enum dcgu_hw_module {
31 DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */
32
33 DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */
34 DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/
35
36 DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */
37 DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */
38 DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */
39 DCGU_HW_MODULE_DVP, /* Selects dig video processing module */
40 DCGU_HW_MODULE_CVE, /* Selects color video encoder module */
41 DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */
42
43 DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */
44 DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */
45
46 DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */
47 DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */
48
49 DCGU_HW_MODULE_UART_1, /* Selects first UART module */
50 DCGU_HW_MODULE_UART_2, /* Selects second UART module */
51
52 DCGU_HW_MODULE_AD, /* Selects audio decoder module */
53 DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */
54 DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/
55 DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */
56
57 DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/
58 DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */
59 DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */
60
61 DCGU_HW_MODULE_USBH, /* Selects USB hub module */
62 DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */
63 DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */
64 DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */
65
66 DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/
67 DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/
68 DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/
69 DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */
70 DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */
71 DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */
72
73 DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/
74 DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/
75
76 DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */
77 DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */
78
79 DCGU_HW_MODULE_COM, /* Selects COM unit module */
80 DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */
81 DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */
82
83 DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/
84 DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */
85 DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */
86 DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */
87
88 DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */
89 DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */
90 DCGU_HW_MODULE_SRAM, /* Selects SRAM module */
91 DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/
92 DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */
93 DCGU_HW_MODULE_SCC, /* Selects SCC module */
94 DCGU_HW_MODULE_MM, /* Selects Memory Manager module */
95 DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */
96 DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */
97 DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */
98 DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */
99 DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/
100};
101
102union dcgu_clk_en1 {
103 u32 reg;
104 struct {
105 u32 res1:8; /* reserved */
106 u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */
107 u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */
108 u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */
109 u32 en_clksmc:1; /* Enable bit for clksmc (#) */
110 u32 en_clkebi:1; /* Enable bit for clkebi (#) */
111 u32 en_usbpll:1; /* Enable bit for the USB PLL */
112 u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */
113 u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */
114 u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */
115 u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */
116 u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */
117 u32 res2:3; /* reserved */
118 u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */
119 u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */
120 u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */
121 u32 en_clkad:1; /* Enable bit for clkad (#) */
122 u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */
123 u32 en_clktsd:1; /* Enable bit for clktsd (#) */
124 u32 en_clkga:1; /* Enable bit for clkga (#) */
125 u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */
126 u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */
127 u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */
128 } bits;
129};
130
131union dcgu_clk_en2 {
132 u32 reg;
133 struct {
134 u32 res1:31; /* reserved */
135 u32 en_clkcpu:1; /* Enable bit for clkcpu */
136 } bits;
137};
138
139union dcgu_reset_unit1 {
140 u32 reg;
141 struct {
142 u32 res1:1;
143 u32 swreset_clkmsmc:1;
144 u32 swreset_clkssi_s:1;
145 u32 swreset_clkssi_m:1;
146 u32 swreset_clksmc:1;
147 u32 swreset_clkebi:1;
148 u32 swreset_clkusb60:1;
149 u32 swreset_clkusb24:1;
150 u32 swreset_clkuart2:1;
151 u32 swreset_clkuart1:1;
152 u32 swreset_pwm:1;
153 u32 swreset_gpt:1;
154 u32 swreset_i2c2:1;
155 u32 swreset_i2c1:1;
156 u32 swreset_gpio2:1;
157 u32 swreset_gpio1:1;
158 u32 swreset_clkcpu:1;
159 u32 res2:2;
160 u32 swreset_clk_i2s_dly:1;
161 u32 swreset_clk_scc_abp:1;
162 u32 swreset_clk_dtv_spdo:1;
163 u32 swreset_clkad:1;
164 u32 swreset_clkmvd:1;
165 u32 swreset_clktsd:1;
166 u32 swreset_clktsio:1;
167 u32 swreset_clkga:1;
168 u32 swreset_clkmpc:1;
169 u32 swreset_clkcve:1;
170 u32 swreset_clkdvp:1;
171 u32 swreset_clkmr2:1;
172 u32 swreset_clkmr1:1;
173 } bits;
174};
175
176int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
177int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
178
179#endif /* _DCGU_H */