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git01.mediatek.com / filogic / uboot / 1234ce736c362fe962aba9f3a07ba4601bf69e4b / . / arch / arm / include / asm / arch-mx6 / mxc_hdmi.h
blob: 9dccb3fef5f1f3565c9b3ea88177f48fc77c99cd [file] [log] [blame]
Eric Nelsonb013f372012-10-03 07:28:42 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef __MXC_HDMI_H__
22#define __MXC_HDMI_H__
23
24/*
25 * Hdmi controller registers
26 */
Fabio Estevam83918e52013-02-28 14:35:02 +0000[diff] [blame]27struct hdmi_regs {
28 /*Identification Registers */
29 u8 design_id; /* 0x000 */
30 u8 revision_id; /* 0x001 */
31 u8 product_id0; /* 0x002 */
32 u8 product_id1; /* 0x003 */
33 u8 config0_id; /* 0x004 */
34 u8 config1_id; /* 0x005 */
35 u8 config2_id; /* 0x006 */
36 u8 config3_id; /* 0x007 */
37 u8 reserved1[0xf8];
38 /* Interrupt Registers */
39 u8 ih_fc_stat0; /* 0x100 */
40 u8 ih_fc_stat1; /* 0x101 */
41 u8 ih_fc_stat2; /* 0x102 */
42 u8 ih_as_stat0; /* 0x103 */
43 u8 ih_phy_stat0; /* 0x104 */
44 u8 ih_i2cm_stat0; /* 0x105 */
45 u8 ih_cec_stat0; /* 0x106 */
46 u8 ih_vp_stat0; /* 0x107 */
47 u8 ih_i2cmphy_stat0; /* 0x108 */
48 u8 ih_ahbdmaaud_stat0; /* 0x109 */
49 u8 reserved2[0x76];
50 u8 ih_mute_fc_stat0; /* 0x180 */
51 u8 ih_mute_fc_stat1; /* 0x181 */
52 u8 ih_mute_fc_stat2; /* 0x182 */
53 u8 ih_mute_as_stat0; /* 0x183 */
54 u8 ih_mute_phy_stat0; /* 0x184 */
55 u8 ih_mute_i2cm_stat0; /* 0x185 */
56 u8 ih_mute_cec_stat0; /* 0x186 */
57 u8 ih_mute_vp_stat0; /* 0x187 */
58 u8 ih_mute_i2cmphy_stat0; /* 0x188 */
59 u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */
60 u8 reserved3[0x75];
61 u8 ih_mute; /* 0x1ff */
62 /* Video Sample Registers */
63 u8 tx_invid0; /* 0x200 */
64 u8 tx_instuffing; /* 0x201 */
65 u8 tx_gydata0; /* 0x202 */
66 u8 tx_gydata1; /* 0x203 */
67 u8 tx_rcrdata0; /* 0x204 */
68 u8 tx_rcrdata1; /* 0x205 */
69 u8 tx_bcbdata0; /* 0x206 */
70 u8 tx_bcbdata1; /* 0x207 */
71 u8 reserved4[0x5f8];
72 /* Video Packetizer Registers */
73 u8 vp_status; /* 0x800 */
74 u8 vp_pr_cd; /* 0x801 */
75 u8 vp_stuff; /* 0x802 */
76 u8 vp_remap; /* 0x803 */
77 u8 vp_conf; /* 0x804 */
78 u8 vp_stat; /* 0x805 */
79 u8 vp_int; /* 0x806 */
80 u8 vp_mask; /* 0x807 */
81 u8 vp_pol; /* 0x808 */
82 u8 reserved5[0x7f7];
83 /* Frame Composer Registers */
84 u8 fc_invidconf; /* 0x1000 */
85 u8 fc_inhactv0; /* 0x1001 */
86 u8 fc_inhactv1; /* 0x1002 */
87 u8 fc_inhblank0; /* 0x1003 */
88 u8 fc_inhblank1; /* 0x1004 */
89 u8 fc_invactv0; /* 0x1005 */
90 u8 fc_invactv1; /* 0x1006 */
91 u8 fc_invblank; /* 0x1007 */
92 u8 fc_hsyncindelay0; /* 0x1008 */
93 u8 fc_hsyncindelay1; /* 0x1009 */
94 u8 fc_hsyncinwidth0; /* 0x100a */
95 u8 fc_hsyncinwidth1; /* 0x100b */
96 u8 fc_vsyncindelay; /* 0x100c */
97 u8 fc_vsyncinwidth; /* 0x100d */
98 u8 fc_infreq0; /* 0x100e */
99 u8 fc_infreq1; /* 0x100f */
100 u8 fc_infreq2; /* 0x1010 */
101 u8 fc_ctrldur; /* 0x1011 */
102 u8 fc_exctrldur; /* 0x1012 */
103 u8 fc_exctrlspac; /* 0x1013 */
104 u8 fc_ch0pream; /* 0x1014 */
105 u8 fc_ch1pream; /* 0x1015 */
106 u8 fc_ch2pream; /* 0x1016 */
107 u8 fc_aviconf3; /* 0x1017 */
108 u8 fc_gcp; /* 0x1018 */
109 u8 fc_aviconf0; /* 0x1019 */
110 u8 fc_aviconf1; /* 0x101a */
111 u8 fc_aviconf2; /* 0x101b */
112 u8 fc_avivid; /* 0x101c */
113 u8 fc_avietb0; /* 0x101d */
114 u8 fc_avietb1; /* 0x101e */
115 u8 fc_avisbb0; /* 0x101f */
116 u8 fc_avisbb1; /* 0x1020 */
117 u8 fc_avielb0; /* 0x1021 */
118 u8 fc_avielb1; /* 0x1022 */
119 u8 fc_avisrb0; /* 0x1023 */
120 u8 fc_avisrb1; /* 0x1024 */
121 u8 fc_audiconf0; /* 0x1025 */
122 u8 fc_audiconf1; /* 0x1026 */
123 u8 fc_audiconf2; /* 0x1027 */
124 u8 fc_audiconf3; /* 0x1028 */
125 u8 fc_vsdieeeid0; /* 0x1029 */
126 u8 fc_vsdsize; /* 0x102a */
127 u8 reserved6[5];
128 u8 fc_vsdieeeid1; /* 0x1030 */
129 u8 fc_vsdieeeid2; /* 0x1031 */
130 u8 fc_vsdpayload0; /* 0x1032 */
131 u8 fc_vsdpayload1; /* 0x1033 */
132 u8 fc_vsdpayload2; /* 0x1034 */
133 u8 fc_vsdpayload3; /* 0x1035 */
134 u8 fc_vsdpayload4; /* 0x1036 */
135 u8 fc_vsdpayload5; /* 0x1037 */
136 u8 fc_vsdpayload6; /* 0x1038 */
137 u8 fc_vsdpayload7; /* 0x1039 */
138 u8 fc_vsdpayload8; /* 0x103a */
139 u8 fc_vsdpayload9; /* 0x103b */
140 u8 fc_vsdpayload10; /* 0x103c */
141 u8 fc_vsdpayload11; /* 0x103d */
142 u8 fc_vsdpayload12; /* 0x103e */
143 u8 fc_vsdpayload13; /* 0x103f */
144 u8 fc_vsdpayload14; /* 0x1040 */
145 u8 fc_vsdpayload15; /* 0x1041 */
146 u8 fc_vsdpayload16; /* 0x1042 */
147 u8 fc_vsdpayload17; /* 0x1043 */
148 u8 fc_vsdpayload18; /* 0x1044 */
149 u8 fc_vsdpayload19; /* 0x1045 */
150 u8 fc_vsdpayload20; /* 0x1046 */
151 u8 fc_vsdpayload21; /* 0x1047 */
152 u8 fc_vsdpayload22; /* 0x1048 */
153 u8 fc_vsdpayload23; /* 0x1049 */
154 u8 fc_spdvendorname0; /* 0x104a */
155 u8 fc_spdvendorname1; /* 0x104b */
156 u8 fc_spdvendorname2; /* 0x104c */
157 u8 fc_spdvendorname3; /* 0x104d */
158 u8 fc_spdvendorname4; /* 0x104e */
159 u8 fc_spdvendorname5; /* 0x104f */
160 u8 fc_spdvendorname6; /* 0x1050 */
161 u8 fc_spdvendorname7; /* 0x1051 */
162 u8 fc_sdpproductname0; /* 0x1052 */
163 u8 fc_sdpproductname1; /* 0x1053 */
164 u8 fc_sdpproductname2; /* 0x1054 */
165 u8 fc_sdpproductname3; /* 0x1055 */
166 u8 fc_sdpproductname4; /* 0x1056 */
167 u8 fc_sdpproductname5; /* 0x1057 */
168 u8 fc_sdpproductname6; /* 0x1058 */
169 u8 fc_sdpproductname7; /* 0x1059 */
170 u8 fc_sdpproductname8; /* 0x105a */
171 u8 fc_sdpproductname9; /* 0x105b */
172 u8 fc_sdpproductname10; /* 0x105c */
173 u8 fc_sdpproductname11; /* 0x105d */
174 u8 fc_sdpproductname12; /* 0x105e */
175 u8 fc_sdpproductname13; /* 0x105f */
176 u8 fc_sdpproductname14; /* 0x1060 */
177 u8 fc_spdproductname15; /* 0x1061 */
178 u8 fc_spddeviceinf; /* 0x1062 */
179 u8 fc_audsconf; /* 0x1063 */
180 u8 fc_audsstat; /* 0x1064 */
181 u8 reserved7[0xb];
182 u8 fc_datach0fill; /* 0x1070 */
183 u8 fc_datach1fill; /* 0x1071 */
184 u8 fc_datach2fill; /* 0x1072 */
185 u8 fc_ctrlqhigh; /* 0x1073 */
186 u8 fc_ctrlqlow; /* 0x1074 */
187 u8 fc_acp0; /* 0x1075 */
188 u8 fc_acp28; /* 0x1076 */
189 u8 fc_acp27; /* 0x1077 */
190 u8 fc_acp26; /* 0x1078 */
191 u8 fc_acp25; /* 0x1079 */
192 u8 fc_acp24; /* 0x107a */
193 u8 fc_acp23; /* 0x107b */
194 u8 fc_acp22; /* 0x107c */
195 u8 fc_acp21; /* 0x107d */
196 u8 fc_acp20; /* 0x107e */
197 u8 fc_acp19; /* 0x107f */
198 u8 fc_acp18; /* 0x1080 */
199 u8 fc_acp17; /* 0x1081 */
200 u8 fc_acp16; /* 0x1082 */
201 u8 fc_acp15; /* 0x1083 */
202 u8 fc_acp14; /* 0x1084 */
203 u8 fc_acp13; /* 0x1085 */
204 u8 fc_acp12; /* 0x1086 */
205 u8 fc_acp11; /* 0x1087 */
206 u8 fc_acp10; /* 0x1088 */
207 u8 fc_acp9; /* 0x1089 */
208 u8 fc_acp8; /* 0x108a */
209 u8 fc_acp7; /* 0x108b */
210 u8 fc_acp6; /* 0x108c */
211 u8 fc_acp5; /* 0x108d */
212 u8 fc_acp4; /* 0x108e */
213 u8 fc_acp3; /* 0x108f */
214 u8 fc_acp2; /* 0x1090 */
215 u8 fc_acp1; /* 0x1091 */
216 u8 fc_iscr1_0; /* 0x1092 */
217 u8 fc_iscr1_16; /* 0x1093 */
218 u8 fc_iscr1_15; /* 0x1094 */
219 u8 fc_iscr1_14; /* 0x1095 */
220 u8 fc_iscr1_13; /* 0x1096 */
221 u8 fc_iscr1_12; /* 0x1097 */
222 u8 fc_iscr1_11; /* 0x1098 */
223 u8 fc_iscr1_10; /* 0x1099 */
224 u8 fc_iscr1_9; /* 0x109a */
225 u8 fc_iscr1_8; /* 0x109b */
226 u8 fc_iscr1_7; /* 0x109c */
227 u8 fc_iscr1_6; /* 0x109d */
228 u8 fc_iscr1_5; /* 0x109e */
229 u8 fc_iscr1_4; /* 0x109f */
230 u8 fc_iscr1_3; /* 0x10a0 */
231 u8 fc_iscr1_2; /* 0x10a1 */
232 u8 fc_iscr1_1; /* 0x10a2 */
233 u8 fc_iscr2_15; /* 0x10a3 */
234 u8 fc_iscr2_14; /* 0x10a4 */
235 u8 fc_iscr2_13; /* 0x10a5 */
236 u8 fc_iscr2_12; /* 0x10a6 */
237 u8 fc_iscr2_11; /* 0x10a7 */
238 u8 fc_iscr2_10; /* 0x10a8 */
239 u8 fc_iscr2_9; /* 0x10a9 */
240 u8 fc_iscr2_8; /* 0x10aa */
241 u8 fc_iscr2_7; /* 0x10ab */
242 u8 fc_iscr2_6; /* 0x10ac */
243 u8 fc_iscr2_5; /* 0x10ad */
244 u8 fc_iscr2_4; /* 0x10ae */
245 u8 fc_iscr2_3; /* 0x10af */
246 u8 fc_iscr2_2; /* 0x10b0 */
247 u8 fc_iscr2_1; /* 0x10b1 */
248 u8 fc_iscr2_0; /* 0x10b2 */
249 u8 fc_datauto0; /* 0x10b3 */
250 u8 fc_datauto1; /* 0x10b4 */
251 u8 fc_datauto2; /* 0x10b5 */
252 u8 fc_datman; /* 0x10b6 */
253 u8 fc_datauto3; /* 0x10b7 */
254 u8 fc_rdrb0; /* 0x10b8 */
255 u8 fc_rdrb1; /* 0x10b9 */
256 u8 fc_rdrb2; /* 0x10ba */
257 u8 fc_rdrb3; /* 0x10bb */
258 u8 fc_rdrb4; /* 0x10bc */
259 u8 fc_rdrb5; /* 0x10bd */
260 u8 fc_rdrb6; /* 0x10be */
261 u8 fc_rdrb7; /* 0x10bf */
262 u8 reserved8[0x10];
263 u8 fc_stat0; /* 0x10d0 */
264 u8 fc_int0; /* 0x10d1 */
265 u8 fc_mask0; /* 0x10d2 */
266 u8 fc_pol0; /* 0x10d3 */
267 u8 fc_stat1; /* 0x10d4 */
268 u8 fc_int1; /* 0x10d5 */
269 u8 fc_mask1; /* 0x10d6 */
270 u8 fc_pol1; /* 0x10d7 */
271 u8 fc_stat2; /* 0x10d8 */
272 u8 fc_int2; /* 0x10d9 */
273 u8 fc_mask2; /* 0x10da */
274 u8 fc_pol2; /* 0x10db */
275 u8 reserved9[0x4];
276 u8 fc_prconf; /* 0x10e0 */
277 u8 reserved10[0x1f];
278 u8 fc_gmd_stat; /* 0x1100 */
279 u8 fc_gmd_en; /* 0x1101 */
280 u8 fc_gmd_up; /* 0x1102 */
281 u8 fc_gmd_conf; /* 0x1103 */
282 u8 fc_gmd_hb; /* 0x1104 */
283 u8 fc_gmd_pb0; /* 0x1105 */
284 u8 fc_gmd_pb1; /* 0x1106 */
285 u8 fc_gmd_pb2; /* 0x1107 */
286 u8 fc_gmd_pb3; /* 0x1108 */
287 u8 fc_gmd_pb4; /* 0x1109 */
288 u8 fc_gmd_pb5; /* 0x110a */
289 u8 fc_gmd_pb6; /* 0x110b */
290 u8 fc_gmd_pb7; /* 0x110c */
291 u8 fc_gmd_pb8; /* 0x110d */
292 u8 fc_gmd_pb9; /* 0x110e */
293 u8 fc_gmd_pb10; /* 0x110f */
294 u8 fc_gmd_pb11; /* 0x1110 */
295 u8 fc_gmd_pb12; /* 0x1111 */
296 u8 fc_gmd_pb13; /* 0x1112 */
297 u8 fc_gmd_pb14; /* 0x1113 */
298 u8 fc_gmd_pb15; /* 0x1114 */
299 u8 fc_gmd_pb16; /* 0x1115 */
300 u8 fc_gmd_pb17; /* 0x1116 */
301 u8 fc_gmd_pb18; /* 0x1117 */
302 u8 fc_gmd_pb19; /* 0x1118 */
303 u8 fc_gmd_pb20; /* 0x1119 */
304 u8 fc_gmd_pb21; /* 0x111a */
305 u8 fc_gmd_pb22; /* 0x111b */
306 u8 fc_gmd_pb23; /* 0x111c */
307 u8 fc_gmd_pb24; /* 0x111d */
308 u8 fc_gmd_pb25; /* 0x111e */
309 u8 fc_gmd_pb26; /* 0x111f */
310 u8 fc_gmd_pb27; /* 0x1120 */
311 u8 reserved11[0xdf];
312 u8 fc_dbgforce; /* 0x1200 */
313 u8 fc_dbgaud0ch0; /* 0x1201 */
314 u8 fc_dbgaud1ch0; /* 0x1202 */
315 u8 fc_dbgaud2ch0; /* 0x1203 */
316 u8 fc_dbgaud0ch1; /* 0x1204 */
317 u8 fc_dbgaud1ch1; /* 0x1205 */
318 u8 fc_dbgaud2ch1; /* 0x1206 */
319 u8 fc_dbgaud0ch2; /* 0x1207 */
320 u8 fc_dbgaud1ch2; /* 0x1208 */
321 u8 fc_dbgaud2ch2; /* 0x1209 */
322 u8 fc_dbgaud0ch3; /* 0x120a */
323 u8 fc_dbgaud1ch3; /* 0x120b */
324 u8 fc_dbgaud2ch3; /* 0x120c */
325 u8 fc_dbgaud0ch4; /* 0x120d */
326 u8 fc_dbgaud1ch4; /* 0x120e */
327 u8 fc_dbgaud2ch4; /* 0x120f */
328 u8 fc_dbgaud0ch5; /* 0x1210 */
329 u8 fc_dbgaud1ch5; /* 0x1211 */
330 u8 fc_dbgaud2ch5; /* 0x1212 */
331 u8 fc_dbgaud0ch6; /* 0x1213 */
332 u8 fc_dbgaud1ch6; /* 0x1214 */
333 u8 fc_dbgaud2ch6; /* 0x1215 */
334 u8 fc_dbgaud0ch7; /* 0x1216 */
335 u8 fc_dbgaud1ch7; /* 0x1217 */
336 u8 fc_dbgaud2ch7; /* 0x1218 */
337 u8 fc_dbgtmds0; /* 0x1219 */
338 u8 fc_dbgtmds1; /* 0x121a */
339 u8 fc_dbgtmds2; /* 0x121b */
340 u8 reserved12[0x1de4];
341 /* Hdmi Source Phy Registers */
342 u8 phy_conf0; /* 0x3000 */
343 u8 phy_tst0; /* 0x3001 */
344 u8 phy_tst1; /* 0x3002 */
345 u8 phy_tst2; /* 0x3003 */
346 u8 phy_stat0; /* 0x3004 */
347 u8 phy_int0; /* 0x3005 */
348 u8 phy_mask0; /* 0x3006 */
349 u8 phy_pol0; /* 0x3007 */
350 u8 reserved13[0x18];
351 /* Hdmi Master Phy Registers */
352 u8 phy_i2cm_slave_addr; /* 0x3020 */
353 u8 phy_i2cm_address_addr; /* 0x3021 */
354 u8 phy_i2cm_datao_1_addr; /* 0x3022 */
355 u8 phy_i2cm_datao_0_addr; /* 0x3023 */
356 u8 phy_i2cm_datai_1_addr; /* 0x3024 */
357 u8 phy_i2cm_datai_0_addr; /* 0x3025 */
358 u8 phy_i2cm_operation_addr; /* 0x3026 */
359 u8 phy_i2cm_int_addr; /* 0x3027 */
360 u8 phy_i2cm_ctlint_addr; /* 0x3028 */
361 u8 phy_i2cm_div_addr; /* 0x3029 */
362 u8 phy_i2cm_softrstz_addr; /* 0x302a */
363 u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */
364 u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */
365 u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */
366 u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */
367 u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */
368 u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */
369 u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */
370 u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */
371 u8 reserved14[0xcd];
372 /* Audio Sampler Registers */
373 u8 aud_conf0; /* 0x3100 */
374 u8 aud_conf1; /* 0x3101 */
375 u8 aud_int; /* 0x3102 */
376 u8 aud_conf2; /* 0x3103 */
377 u8 reserved15[0xfc];
378 u8 aud_n1; /* 0x3200 */
379 u8 aud_n2; /* 0x3201 */
380 u8 aud_n3; /* 0x3202 */
381 u8 aud_cts1; /* 0x3203 */
382 u8 aud_cts2; /* 0x3204 */
383 u8 aud_cts3; /* 0x3205 */
384 u8 aud_inputclkfs; /* 0x3206 */
385 u8 reserved16[0xfb];
386 u8 aud_spdifint; /* 0x3302 */
387 u8 reserved17[0xfd];
388 u8 aud_conf0_hbr; /* 0x3400 */
389 u8 aud_hbr_status; /* 0x3401 */
390 u8 aud_hbr_int; /* 0x3402 */
391 u8 aud_hbr_pol; /* 0x3403 */
392 u8 aud_hbr_mask; /* 0x3404 */
393 u8 reserved18[0xfb];
394 /*
395 * Generic Parallel Audio Interface Registers
396 * Not used as GPAUD interface is not enabled in hw
397 */
398 u8 gp_conf0; /* 0x3500 */
399 u8 gp_conf1; /* 0x3501 */
400 u8 gp_conf2; /* 0x3502 */
401 u8 gp_stat; /* 0x3503 */
402 u8 gp_int; /* 0x3504 */
403 u8 gp_mask; /* 0x3505 */
404 u8 gp_pol; /* 0x3506 */
405 u8 reserved19[0xf9];
406 /* Audio DMA Registers */
407 u8 ahb_dma_conf0; /* 0x3600 */
408 u8 ahb_dma_start; /* 0x3601 */
409 u8 ahb_dma_stop; /* 0x3602 */
410 u8 ahb_dma_thrsld; /* 0x3603 */
411 u8 ahb_dma_straddr0; /* 0x3604 */
412 u8 ahb_dma_straddr1; /* 0x3605 */
413 u8 ahb_dma_straddr2; /* 0x3606 */
414 u8 ahb_dma_straddr3; /* 0x3607 */
415 u8 ahb_dma_stpaddr0; /* 0x3608 */
416 u8 ahb_dma_stpaddr1; /* 0x3609 */
417 u8 ahb_dma_stpaddr2; /* 0x360a */
418 u8 ahb_dma_stpaddr3; /* 0x360b */
419 u8 ahb_dma_bstaddr0; /* 0x360c */
420 u8 ahb_dma_bstaddr1; /* 0x360d */
421 u8 ahb_dma_bstaddr2; /* 0x360e */
422 u8 ahb_dma_bstaddr3; /* 0x360f */
423 u8 ahb_dma_mblength0; /* 0x3610 */
424 u8 ahb_dma_mblength1; /* 0x3611 */
425 u8 ahb_dma_stat; /* 0x3612 */
426 u8 ahb_dma_int; /* 0x3613 */
427 u8 ahb_dma_mask; /* 0x3614 */
428 u8 ahb_dma_pol; /* 0x3615 */
429 u8 ahb_dma_conf1; /* 0x3616 */
430 u8 ahb_dma_buffstat; /* 0x3617 */
431 u8 ahb_dma_buffint; /* 0x3618 */
432 u8 ahb_dma_buffmask; /* 0x3619 */
433 u8 ahb_dma_buffpol; /* 0x361a */
434 u8 reserved20[0x9e5];
435 /* Main Controller Registers */
436 u8 mc_sfrdiv; /* 0x4000 */
437 u8 mc_clkdis; /* 0x4001 */
438 u8 mc_swrstz; /* 0x4002 */
439 u8 mc_opctrl; /* 0x4003 */
440 u8 mc_flowctrl; /* 0x4004 */
441 u8 mc_phyrstz; /* 0x4005 */
442 u8 mc_lockonclock; /* 0x4006 */
443 u8 mc_heacphy_rst; /* 0x4007 */
444 u8 reserved21[0xf8];
445 /* Colorspace Converter Registers */
446 u8 csc_cfg; /* 0x4100 */
447 u8 csc_scale; /* 0x4101 */
448 u8 csc_coef_a1_msb; /* 0x4102 */
449 u8 csc_coef_a1_lsb; /* 0x4103 */
450 u8 csc_coef_a2_msb; /* 0x4104 */
451 u8 csc_coef_a2_lsb; /* 0x4105 */
452 u8 csc_coef_a3_msb; /* 0x4106 */
453 u8 csc_coef_a3_lsb; /* 0x4107 */
454 u8 csc_coef_a4_msb; /* 0x4108 */
455 u8 csc_coef_a4_lsb; /* 0x4109 */
456 u8 csc_coef_b1_msb; /* 0x410a */
457 u8 csc_coef_b1_lsb; /* 0x410b */
458 u8 csc_coef_b2_msb; /* 0x410c */
459 u8 csc_coef_b2_lsb; /* 0x410d */
460 u8 csc_coef_b3_msb; /* 0x410e */
461 u8 csc_coef_b3_lsb; /* 0x410f */
462 u8 csc_coef_b4_msb; /* 0x4110 */
463 u8 csc_coef_b4_lsb; /* 0x4111 */
464 u8 csc_coef_c1_msb; /* 0x4112 */
465 u8 csc_coef_c1_lsb; /* 0x4113 */
466 u8 csc_coef_c2_msb; /* 0x4114 */
467 u8 csc_coef_c2_lsb; /* 0x4115 */
468 u8 csc_coef_c3_msb; /* 0x4116 */
469 u8 csc_coef_c3_lsb; /* 0x4117 */
470 u8 csc_coef_c4_msb; /* 0x4118 */
471 u8 csc_coef_c4_lsb; /* 0x4119 */
472 u8 reserved22[0xee6];
473 /* HDCP Encryption Engine Registers */
474 u8 a_hdcpcfg0; /* 0x5000 */
475 u8 a_hdcpcfg1; /* 0x5001 */
476 u8 a_hdcpobs0; /* 0x5002 */
477 u8 a_hdcpobs1; /* 0x5003 */
478 u8 a_hdcpobs2; /* 0x5004 */
479 u8 a_hdcpobs3; /* 0x5005 */
480 u8 a_apiintclr; /* 0x5006 */
481 u8 a_apiintstat; /* 0x5007 */
482 u8 a_apiintmsk; /* 0x5008 */
483 u8 a_vidpolcfg; /* 0x5009 */
484 u8 a_oesswcfg; /* 0x500a */
485 u8 a_timer1setup0; /* 0x500b */
486 u8 a_timer1setup1; /* 0x500c */
487 u8 a_timer2setup0; /* 0x500d */
488 u8 a_timer2setup1; /* 0x500e */
489 u8 a_100mscfg; /* 0x500f */
490 u8 a_2scfg0; /* 0x5010 */
491 u8 a_2scfg1; /* 0x5011 */
492 u8 a_5scfg0; /* 0x5012 */
493 u8 a_5scfg1; /* 0x5013 */
494 u8 a_srmverlsb; /* 0x5014 */
495 u8 a_srmvermsb; /* 0x5015 */
496 u8 a_srmctrl; /* 0x5016 */
497 u8 a_sfrsetup; /* 0x5017 */
498 u8 a_i2chsetup; /* 0x5018 */
499 u8 a_intsetup; /* 0x5019 */
500 u8 a_presetup; /* 0x501a */
501 u8 reserved23[0x5];
502 u8 a_srm_base; /* 0x5020 */
503 u8 reserved24[0x2cdf];
504 /* CEC Engine Registers */
505 u8 cec_ctrl; /* 0x7d00 */
506 u8 cec_stat; /* 0x7d01 */
507 u8 cec_mask; /* 0x7d02 */
508 u8 cec_polarity; /* 0x7d03 */
509 u8 cec_int; /* 0x7d04 */
510 u8 cec_addr_l; /* 0x7d05 */
511 u8 cec_addr_h; /* 0x7d06 */
512 u8 cec_tx_cnt; /* 0x7d07 */
513 u8 cec_rx_cnt; /* 0x7d08 */
514 u8 reserved25[0x7];
515 u8 cec_tx_data0; /* 0x7d10 */
516 u8 cec_tx_data1; /* 0x7d11 */
517 u8 cec_tx_data2; /* 0x7d12 */
518 u8 cec_tx_data3; /* 0x7d13 */
519 u8 cec_tx_data4; /* 0x7d14 */
520 u8 cec_tx_data5; /* 0x7d15 */
521 u8 cec_tx_data6; /* 0x7d16 */
522 u8 cec_tx_data7; /* 0x7d17 */
523 u8 cec_tx_data8; /* 0x7d18 */
524 u8 cec_tx_data9; /* 0x7d19 */
525 u8 cec_tx_data10; /* 0x7d1a */
526 u8 cec_tx_data11; /* 0x7d1b */
527 u8 cec_tx_data12; /* 0x7d1c */
528 u8 cec_tx_data13; /* 0x7d1d */
529 u8 cec_tx_data14; /* 0x7d1e */
530 u8 cec_tx_data15; /* 0x7d1f */
531 u8 cec_rx_data0; /* 0x7d20 */
532 u8 cec_rx_data1; /* 0x7d21 */
533 u8 cec_rx_data2; /* 0x7d22 */
534 u8 cec_rx_data3; /* 0x7d23 */
535 u8 cec_rx_data4; /* 0x7d24 */
536 u8 cec_rx_data5; /* 0x7d25 */
537 u8 cec_rx_data6; /* 0x7d26 */
538 u8 cec_rx_data7; /* 0x7d27 */
539 u8 cec_rx_data8; /* 0x7d28 */
540 u8 cec_rx_data9; /* 0x7d29 */
541 u8 cec_rx_data10; /* 0x7d2a */
542 u8 cec_rx_data11; /* 0x7d2b */
543 u8 cec_rx_data12; /* 0x7d2c */
544 u8 cec_rx_data13; /* 0x7d2d */
545 u8 cec_rx_data14; /* 0x7d2e */
546 u8 cec_rx_data15; /* 0x7d2f */
547 u8 cec_lock; /* 0x7d30 */
548 u8 cec_wkupctrl; /* 0x7d31 */
549 u8 reserved26[0xce];
550 /* I2C Master Registers (E-DDC) */
551 u8 i2cm_slave; /* 0x7e00 */
552 u8 i2cmess; /* 0x7e01 */
553 u8 i2cm_datao; /* 0x7e02 */
554 u8 i2cm_datai; /* 0x7e03 */
555 u8 i2cm_operation; /* 0x7e04 */
556 u8 i2cm_int; /* 0x7e05 */
557 u8 i2cm_ctlint; /* 0x7e06 */
558 u8 i2cm_div; /* 0x7e07 */
559 u8 i2cm_segaddr; /* 0x7e08 */
560 u8 i2cm_softrstz; /* 0x7e09 */
561 u8 i2cm_segptr; /* 0x7e0a */
562 u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */
563 u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */
564 u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */
565 u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */
566 u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */
567 u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */
568 u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */
569 u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */
570 u8 reserved27[0x1ed];
571 /* Random Number Generator Registers (RNG) */
572 u8 rng_base; /* 0x8000 */
573};
Eric Nelsonb013f372012-10-03 07:28:42 +0000[diff] [blame]574
575/*
576 * Register field definitions
577 */
578enum {
579/* IH_FC_INT2 field values */
580 HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
581 HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
582 HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
583
584/* IH_FC_STAT2 field values */
585 HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
586 HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
587 HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
588
589/* IH_PHY_STAT0 field values */
590 HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
591 HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
592 HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
593 HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
594 HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
595 HDMI_IH_PHY_STAT0_HPD = 0x1,
596
597/* IH_MUTE_I2CMPHY_STAT0 field values */
598 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
599 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
600
601/* IH_AHBDMAAUD_STAT0 field values */
602 HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
603 HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
604 HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
605 HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
606 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
607 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
608
609/* IH_MUTE_FC_STAT2 field values */
610 HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
611 HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
612 HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
613
614/* IH_MUTE_AHBDMAAUD_STAT0 field values */
615 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
616 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
617 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
618 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
619 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
620 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
621
622/* IH_MUTE field values */
623 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
624 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
625
626/* TX_INVID0 field values */
627 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
628 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
629 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
630 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
631 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
632
633/* TX_INSTUFFING field values */
634 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
635 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
636 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
637 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
638 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
639 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
640 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
641 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
642 HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
643
644/* VP_PR_CD field values */
645 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
646 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
647 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
648 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
649
650/* VP_STUFF field values */
651 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
652 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
653 HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
654 HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
655 HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
656 HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
657 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
658 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
659 HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
660 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
661 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
662 HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
663 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
664 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
665 HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
666
667/* VP_CONF field values */
668 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
669 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
670 HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
671 HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
672 HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
673 HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
674 HDMI_VP_CONF_PR_EN_MASK = 0x10,
675 HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
676 HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
677 HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
678 HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
679 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
680 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
681 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
682 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
683 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
684 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
685 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
686 HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
687
688/* VP_REMAP field values */
689 HDMI_VP_REMAP_MASK = 0x3,
690 HDMI_VP_REMAP_YCC422_24bit = 0x2,
691 HDMI_VP_REMAP_YCC422_20bit = 0x1,
692 HDMI_VP_REMAP_YCC422_16bit = 0x0,
693
694/* FC_INVIDCONF field values */
695 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
696 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
697 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
698 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
699 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
700 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
701 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
702 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
703 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
704 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
705 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
706 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
707 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
708 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
709 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
710 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
711 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
712 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
713 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
714 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
715 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
716
717/* FC_AUDICONF0 field values */
718 HDMI_FC_AUDICONF0_CC_OFFSET = 4,
719 HDMI_FC_AUDICONF0_CC_MASK = 0x70,
720 HDMI_FC_AUDICONF0_CT_OFFSET = 0,
721 HDMI_FC_AUDICONF0_CT_MASK = 0xF,
722
723/* FC_AUDICONF1 field values */
724 HDMI_FC_AUDICONF1_SS_OFFSET = 3,
725 HDMI_FC_AUDICONF1_SS_MASK = 0x18,
726 HDMI_FC_AUDICONF1_SF_OFFSET = 0,
727 HDMI_FC_AUDICONF1_SF_MASK = 0x7,
728
729/* FC_AUDICONF3 field values */
730 HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
731 HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
732 HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
733 HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
734 HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
735 HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
736
737/* FC_AUDSCHNLS0 field values */
738 HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
739 HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
740 HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
741 HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
742
743/* FC_AUDSCHNLS3-6 field values */
744 HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
745 HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
746 HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
747 HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
748 HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
749 HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
750 HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
751 HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
752
753 HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
754 HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
755 HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
756 HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
757 HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
758 HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
759 HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
760 HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
761
762/* HDMI_FC_AUDSCHNLS7 field values */
763 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
764 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
765
766/* HDMI_FC_AUDSCHNLS8 field values */
767 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
768 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
769 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
770 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
771
772/* FC_AUDSCONF field values */
773 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
774 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
775 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
776 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
777 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
778 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
779
780/* FC_STAT2 field values */
781 HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
782 HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
783 HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
784
785/* FC_INT2 field values */
786 HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
787 HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
788 HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
789
790/* FC_MASK2 field values */
791 HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
792 HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
793 HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
794
795/* FC_PRCONF field values */
796 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
797 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
798 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
799 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
800
801/* FC_AVICONF0-FC_AVICONF3 field values */
802 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
803 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
804 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
805 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
806 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
807 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
808 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
809 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
810 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
811 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
812 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
813 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
814 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
815 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
816 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
817 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
818
819 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
820 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
821 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
822 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
823 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
824 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
825 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
826 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
827 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
828 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
829 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
830 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
831 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
832 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
833
834 HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
835 HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
836 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
837 HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
838 HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
839 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
840 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
841 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
842 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
843 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
844 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
845 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
846 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
847 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
848 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
849 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
850 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
851 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
852
853 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
854 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
855 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
856 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
857 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
858 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
859 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
860 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
861
862/* FC_DBGFORCE field values */
863 HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
864 HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
865
866/* PHY_CONF0 field values */
867 HDMI_PHY_CONF0_PDZ_MASK = 0x80,
868 HDMI_PHY_CONF0_PDZ_OFFSET = 7,
869 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
870 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
871 HDMI_PHY_CONF0_SPARECTRL = 0x20,
872 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
873 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
874 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
875 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
876 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
877 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
878 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
879 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
880 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
881 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
882
883/* PHY_TST0 field values */
884 HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
885 HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
886 HDMI_PHY_TST0_TSTEN_MASK = 0x10,
887 HDMI_PHY_TST0_TSTEN_OFFSET = 4,
888 HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
889 HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
890
891/* PHY_STAT0 field values */
892 HDMI_PHY_RX_SENSE3 = 0x80,
893 HDMI_PHY_RX_SENSE2 = 0x40,
894 HDMI_PHY_RX_SENSE1 = 0x20,
895 HDMI_PHY_RX_SENSE0 = 0x10,
896 HDMI_PHY_HPD = 0x02,
897 HDMI_PHY_TX_PHY_LOCK = 0x01,
898
899/* PHY_I2CM_SLAVE_ADDR field values */
900 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
901 HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
902
903/* PHY_I2CM_OPERATION_ADDR field values */
904 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
905 HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
906
907/* HDMI_PHY_I2CM_INT_ADDR */
908 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
909 HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
910
911/* HDMI_PHY_I2CM_CTLINT_ADDR */
912 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
913 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
914 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
915 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
916
917/* AUD_CTS3 field values */
918 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
919 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
920 HDMI_AUD_CTS3_N_SHIFT_1 = 0,
921 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
922 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
923 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
924 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
925 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
926 /* note that the CTS3 MANUAL bit has been removed
927 from our part. Can't set it, will read as 0. */
928 HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
929 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
930
931/* AHB_DMA_CONF0 field values */
932 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
933 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
934 HDMI_AHB_DMA_CONF0_HBR = 0x10,
935 HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
936 HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
937 HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
938 HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
939 HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
940 HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
941 HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
942 HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
943
944/* HDMI_AHB_DMA_START field values */
945 HDMI_AHB_DMA_START_START_OFFSET = 0,
946 HDMI_AHB_DMA_START_START_MASK = 0x01,
947
948/* HDMI_AHB_DMA_STOP field values */
949 HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
950 HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
951
952/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
953 HDMI_AHB_DMA_DONE = 0x80,
954 HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
955 HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
956 HDMI_AHB_DMA_ERROR = 0x10,
957 HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
958 HDMI_AHB_DMA_FIFO_FULL = 0x02,
959 HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
960
961/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
962 HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
963 HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
964
965/* MC_CLKDIS field values */
966 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
967 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
968 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
969 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
970 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
971 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
972 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
973
974/* MC_SWRSTZ field values */
975 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
976
977/* MC_FLOWCTRL field values */
978 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
979 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
980 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
981
982/* MC_PHYRSTZ field values */
983 HDMI_MC_PHYRSTZ_ASSERT = 0x0,
984 HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
985
986/* MC_HEACPHY_RST field values */
987 HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
988 HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
989
990/* CSC_CFG field values */
991 HDMI_CSC_CFG_INTMODE_MASK = 0x30,
992 HDMI_CSC_CFG_INTMODE_OFFSET = 4,
993 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
994 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
995 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
996 HDMI_CSC_CFG_DECMODE_MASK = 0x3,
997 HDMI_CSC_CFG_DECMODE_OFFSET = 0,
998 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
999 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
1000 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
1001 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
1002
1003/* CSC_SCALE field values */
1004 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
1005 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
1006 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
1007 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
1008 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
1009 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
1010
1011/* A_HDCPCFG0 field values */
1012 HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
1013 HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
1014 HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
1015 HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
1016 HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
1017 HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
1018 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
1019 HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
1020 HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
1021 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
1022 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
1023 HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
1024 HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
1025 HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
1026 HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
1027 HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
1028 HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
1029 HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
1030 HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
1031 HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
1032 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
1033 HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
1034 HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
1035 HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
1036
1037/* A_HDCPCFG1 field values */
1038 HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
1039 HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
1040 HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
1041 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
1042 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
1043 HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
1044 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
1045 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
1046 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
1047 HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
1048 HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
1049
1050/* A_VIDPOLCFG field values */
1051 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
1052 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
1053 HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
1054 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
1055 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
1056 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
1057 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
1058 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
1059 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
1060 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
1061 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
1062};
1063
1064#endif /* __MXC_HDMI_H__ */