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git01.mediatek.com / filogic / uboot / 1234ce736c362fe962aba9f3a07ba4601bf69e4b / . / arch / arm / cpu / armv7 / u8500 / cpu.c
blob: 6f95c306736c475a8ee5adb345c7b8564a0f49fd [file] [log] [blame]
Mathieu J. Poirier65798982012-07-31 08:59:25 +0000[diff] [blame]1/*
2 * Copyright (C) 2012 Linaro Limited
3 * Mathieu Poirier <mathieu.poirier@linaro.org>
4 *
5 * Based on original code from Joakim Axelsson at ST-Ericsson
6 * (C) Copyright 2010 ST-Ericsson
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/io.h>
29#include <asm/arch/prcmu.h>
Mathieu J. Poirier2d8516bb2012-07-31 08:59:26 +0000[diff] [blame]30#include <asm/arch/clock.h>
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]31#include <asm/arch/hardware.h>
32
33#include <asm/arch/hardware.h>
34
35#define CPUID_DB8500V1 0x411fc091
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]36#define CPUID_DB8500V2 0x412fc091
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]37#define ASICID_DB8500V11 0x008500A1
38
Mathieu J. Poirierbae9ea62012-07-31 08:59:33 +0000[diff] [blame]39#define CACHE_CONTR_BASE 0xA0412000
40/* Cache controller register offsets
41 * as found in ARM's technical reference manual
42 */
43#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
44#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
45#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
46
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]47static unsigned int read_asicid(void);
48
49static inline unsigned int read_cpuid(void)
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]50{
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]51 unsigned int val;
52
53 /* Main ID register (MIDR) */
54 asm("mrc p15, 0, %0, c0, c0, 0"
55 : "=r" (val)
56 :
57 : "cc");
58
59 return val;
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]60}
61
62static int cpu_is_u8500v11(void)
63{
64 return read_asicid() == ASICID_DB8500V11;
65}
Mathieu J. Poirier65798982012-07-31 08:59:25 +0000[diff] [blame]66
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]67static int cpu_is_u8500v2(void)
68{
69 return read_cpuid() == CPUID_DB8500V2;
70}
71
72static unsigned int read_asicid(void)
73{
74 unsigned int *address;
75
76 if (cpu_is_u8500v2())
77 address = (void *) U8500_ASIC_ID_LOC_V2;
78 else
79 address = (void *) U8500_ASIC_ID_LOC_ED_V1;
80
81 return readl(address);
82}
83
Mathieu J. Poirierbae9ea62012-07-31 08:59:33 +0000[diff] [blame]84void cpu_cache_initialization(void)
85{
86 unsigned int value;
87 /* invalidate all cache entries */
88 writel(0xFFFF, CACHE_INVAL_BY_WAY);
89
90 /* ways are set to '0' when they are totally
91 * cleaned and invalidated
92 */
93 do {
94 value = readl(CACHE_INVAL_BY_WAY);
95 } while (value & 0xFF);
96
97 /* Invalidate register 9 D and I lockdown */
98 writel(0xFF, CACHE_LOCKDOWN_BY_D);
99 writel(0xFF, CACHE_LOCKDOWN_BY_I);
100}
101
Mathieu J. Poirier65798982012-07-31 08:59:25 +0000[diff] [blame]102#ifdef CONFIG_ARCH_CPU_INIT
103/*
104 * SOC specific cpu init
105 */
106int arch_cpu_init(void)
107{
108 db8500_prcmu_init();
Mathieu J. Poirier2d8516bb2012-07-31 08:59:26 +0000[diff] [blame]109 db8500_clocks_init();
Mathieu J. Poirier65798982012-07-31 08:59:25 +0000[diff] [blame]110
111 return 0;
112}
113#endif /* CONFIG_ARCH_CPU_INIT */
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]114
115#ifdef CONFIG_MMC
116
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]117int u8500_mmc_power_init(void)
118{
119 int ret;
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]120 int enable, voltage;
121 int ab8500_revision;
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]122
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]123 if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]124 return 0;
125
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]126 /* Get AB8500 revision */
127 ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
128 if (ret < 0)
129 goto out;
130
131 ab8500_revision = ret;
132
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]133 /*
134 * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
135 * card to work. This is done by enabling the regulators in the AB8500
136 * via PRCMU I2C transactions.
137 *
138 * This code is derived from the handling of AB8500_LDO_VAUX3 in
139 * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
140 *
141 * Turn off and delay is required to have it work across soft reboots.
142 */
143
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]144 /* Turn off (read-modify-write) */
145 ret = ab8500_read(AB8500_REGU_CTRL2,
146 AB8500_REGU_VRF1VAUX3_REGU_REG);
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]147 if (ret < 0)
148 goto out;
149
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]150 enable = ret;
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]151
152 /* Turn off */
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]153 ret = ab8500_write(AB8500_REGU_CTRL2,
154 AB8500_REGU_VRF1VAUX3_REGU_REG,
155 enable & ~LDO_VAUX3_ENABLE_MASK);
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]156 if (ret < 0)
157 goto out;
158
159 udelay(10 * 1000);
160
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]161 /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
162 ret = ab8500_read(AB8500_REGU_CTRL2,
163 AB8500_REGU_VRF1VAUX3_SEL_REG);
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]164 if (ret < 0)
165 goto out;
166
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]167 voltage = ret;
168
169 if (ab8500_revision < 0x20) {
170 voltage &= ~LDO_VAUX3_SEL_MASK;
171 voltage |= LDO_VAUX3_SEL_2V9;
172 } else {
173 voltage &= ~LDO_VAUX3_V2_SEL_MASK;
174 voltage |= LDO_VAUX3_V2_SEL_2V91;
175 }
176
177 ret = ab8500_write(AB8500_REGU_CTRL2,
178 AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
179 if (ret < 0)
180 goto out;
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]181
182 /* Turn on the supply */
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000[diff] [blame]183 enable &= ~LDO_VAUX3_ENABLE_MASK;
184 enable |= LDO_VAUX3_ENABLE_VAL;
185
186 ret = ab8500_write(AB8500_REGU_CTRL2,
187 AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
Mathieu J. Poirier0c877652012-07-31 08:59:29 +0000[diff] [blame]188
189out:
190 return ret;
191}
192#endif /* CONFIG_MMC */