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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasut00671d92017-10-09 21:51:10 +02002/*
3 * DHCOM DH-iMX6 PDK board configuration
4 *
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
Marek Vasut00671d92017-10-09 21:51:10 +02006 */
7
8#ifndef __DH_IMX6_CONFIG_H
9#define __DH_IMX6_CONFIG_H
10
11#include <asm/arch/imx-regs.h>
12
Marek Vasut00671d92017-10-09 21:51:10 +020013#include "mx6_common.h"
14
15/*
16 * SPI NOR layout:
17 * 0x00_0000-0x00_ffff ... U-Boot SPL
18 * 0x01_0000-0x0f_ffff ... U-Boot
19 * 0x10_0000-0x10_ffff ... U-Boot env #1
20 * 0x11_0000-0x11_ffff ... U-Boot env #2
21 * 0x12_0000-0x1f_ffff ... UNUSED
22 */
23
24/* SPL */
25#include "imx6_spl.h" /* common IMX6 SPL configuration */
26#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
Marek Vasut00671d92017-10-09 21:51:10 +020027#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
28
29/* Miscellaneous configurable options */
Marek Vasut00671d92017-10-09 21:51:10 +020030
31#define CONFIG_CMDLINE_TAG
32#define CONFIG_SETUP_MEMORY_TAGS
33#define CONFIG_INITRD_TAG
34#define CONFIG_REVISION_TAG
35
Marek Vasut00671d92017-10-09 21:51:10 +020036#define CONFIG_BZIP2
37
38/* Size of malloc() pool */
39#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
40
41/* Bootcounter */
Marek Vasut00671d92017-10-09 21:51:10 +020042#define CONFIG_SYS_BOOTCOUNT_BE
43
44/* FEC ethernet */
Marek Vasut00671d92017-10-09 21:51:10 +020045#define IMX_FEC_BASE ENET_BASE_ADDR
46#define CONFIG_FEC_XCV_TYPE RMII
47#define CONFIG_ETHPRIME "FEC"
48#define CONFIG_FEC_MXC_PHYADDR 0
49#define CONFIG_ARP_TIMEOUT 200UL
50
51/* Fuses */
52#ifdef CONFIG_CMD_FUSE
53#define CONFIG_MXC_OCOTP
54#endif
55
Marek Vasut00671d92017-10-09 21:51:10 +020056/* I2C Configs */
57#define CONFIG_SYS_I2C
58#define CONFIG_SYS_I2C_MXC
59#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
60#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
61#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
62#define CONFIG_SYS_I2C_SPEED 100000
63
64/* MMC Configs */
Marek Vasut00671d92017-10-09 21:51:10 +020065#define CONFIG_FSL_USDHC
66#define CONFIG_SYS_FSL_ESDHC_ADDR 0
67#define CONFIG_SYS_FSL_USDHC_NUM 3
68#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
69
70/* SATA Configs */
71#ifdef CONFIG_CMD_SATA
Marek Vasut00671d92017-10-09 21:51:10 +020072#define CONFIG_SYS_SATA_MAX_DEVICE 1
73#define CONFIG_DWC_AHSATA_PORT_ID 0
74#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
75#define CONFIG_LBA48
Marek Vasut00671d92017-10-09 21:51:10 +020076#endif
77
78/* SPI Flash Configs */
79#ifdef CONFIG_CMD_SF
Marek Vasut00671d92017-10-09 21:51:10 +020080#define CONFIG_SF_DEFAULT_BUS 0
81#define CONFIG_SF_DEFAULT_CS 0
82#define CONFIG_SF_DEFAULT_SPEED 25000000
83#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
84#endif
85
86/* UART */
87#define CONFIG_MXC_UART
88#define CONFIG_MXC_UART_BASE UART1_BASE
Marek Vasut00671d92017-10-09 21:51:10 +020089#define CONFIG_BAUDRATE 115200
90
91/* USB Configs */
92#ifdef CONFIG_CMD_USB
93#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
94#define CONFIG_USB_HOST_ETHER
95#define CONFIG_USB_ETHER_ASIX
96#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
97#define CONFIG_MXC_USB_FLAGS 0
98#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
Marek Vasut861b6892017-10-22 10:22:40 +020099
100/* USB Gadget (DFU, UMS) */
101#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
Marek Vasut861b6892017-10-22 10:22:40 +0200102#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
103#define DFU_DEFAULT_POLL_TIMEOUT 300
104
105/* USB IDs */
106#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
107#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
108#endif
Marek Vasut00671d92017-10-09 21:51:10 +0200109#endif
110
111/* Watchdog */
112#define CONFIG_HW_WATCHDOG
113#define CONFIG_IMX_WATCHDOG
114#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
115
116/* allow to overwrite serial and ethaddr */
117#define CONFIG_ENV_OVERWRITE
118
Marek Vasut00671d92017-10-09 21:51:10 +0200119#define CONFIG_LOADADDR 0x12000000
120#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
121
122#ifndef CONFIG_SPL_BUILD
123#define CONFIG_EXTRA_ENV_SETTINGS \
124 "console=ttymxc0,115200\0" \
125 "fdt_addr=0x18000000\0" \
126 "fdt_high=0xffffffff\0" \
127 "initrd_high=0xffffffff\0" \
128 "kernel_addr_r=0x10008000\0" \
129 "fdt_addr_r=0x13000000\0" \
130 "ramdisk_addr_r=0x18000000\0" \
131 "scriptaddr=0x14000000\0" \
132 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
133 BOOTENV
134
135#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
136
137#define BOOT_TARGET_DEVICES(func) \
138 func(MMC, mmc, 0) \
139 func(MMC, mmc, 2) \
140 func(USB, usb, 1) \
141 func(SATA, sata, 0) \
142 func(DHCP, dhcp, na)
143
144#include <config_distro_bootcmd.h>
145#endif
146
147/* Physical Memory Map */
Marek Vasut00671d92017-10-09 21:51:10 +0200148#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
149
150#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
151#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
152#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
153
154#define CONFIG_SYS_INIT_SP_OFFSET \
155 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
156
157#define CONFIG_SYS_INIT_SP_ADDR \
158 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
159
160#define CONFIG_SYS_MEMTEST_START 0x10000000
161#define CONFIG_SYS_MEMTEST_END 0x20000000
162#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
163
164/* Environment */
165#define CONFIG_ENV_SIZE (16 * 1024)
166#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
167
168#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
169#define CONFIG_ENV_OFFSET (1024 * 1024)
170#define CONFIG_ENV_SECT_SIZE (64 * 1024)
171#define CONFIG_ENV_OFFSET_REDUND \
172 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
173#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
174#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
175#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
176#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
177#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
178#endif
179
180#endif /* __DH_IMX6_CONFIG_H */