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wdenkdd7d41f2002-09-18 20:04:01 +00001/*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * MII Utilities
26 */
27
28#include <common.h>
29#include <command.h>
wdenke44b9112004-04-18 23:32:11 +000030#include <miiphy.h>
31
wdenk61066ec2004-04-18 22:57:51 +000032typedef struct _MII_reg_desc_t {
33 ushort regno;
34 char * name;
35} MII_reg_desc_t;
36
Mike Frysinger4b497472010-10-20 01:06:48 -040037static const MII_reg_desc_t reg_0_5_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +000038 { 0, "PHY control register" },
39 { 1, "PHY status register" },
40 { 2, "PHY ID 1 register" },
41 { 3, "PHY ID 2 register" },
42 { 4, "Autonegotiation advertisement register" },
43 { 5, "Autonegotiation partner abilities register" },
44};
45
46typedef struct _MII_field_desc_t {
47 ushort hi;
48 ushort lo;
49 ushort mask;
50 char * name;
51} MII_field_desc_t;
52
Mike Frysinger4b497472010-10-20 01:06:48 -040053static const MII_field_desc_t reg_0_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +000054 { 15, 15, 0x01, "reset" },
55 { 14, 14, 0x01, "loopback" },
56 { 13, 6, 0x81, "speed selection" }, /* special */
57 { 12, 12, 0x01, "A/N enable" },
58 { 11, 11, 0x01, "power-down" },
59 { 10, 10, 0x01, "isolate" },
60 { 9, 9, 0x01, "restart A/N" },
61 { 8, 8, 0x01, "duplex" }, /* special */
62 { 7, 7, 0x01, "collision test enable" },
63 { 5, 0, 0x3f, "(reserved)" }
64};
65
Mike Frysinger4b497472010-10-20 01:06:48 -040066static const MII_field_desc_t reg_1_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +000067 { 15, 15, 0x01, "100BASE-T4 able" },
68 { 14, 14, 0x01, "100BASE-X full duplex able" },
69 { 13, 13, 0x01, "100BASE-X half duplex able" },
70 { 12, 12, 0x01, "10 Mbps full duplex able" },
71 { 11, 11, 0x01, "10 Mbps half duplex able" },
72 { 10, 10, 0x01, "100BASE-T2 full duplex able" },
73 { 9, 9, 0x01, "100BASE-T2 half duplex able" },
74 { 8, 8, 0x01, "extended status" },
75 { 7, 7, 0x01, "(reserved)" },
76 { 6, 6, 0x01, "MF preamble suppression" },
77 { 5, 5, 0x01, "A/N complete" },
78 { 4, 4, 0x01, "remote fault" },
79 { 3, 3, 0x01, "A/N able" },
80 { 2, 2, 0x01, "link status" },
81 { 1, 1, 0x01, "jabber detect" },
82 { 0, 0, 0x01, "extended capabilities" },
83};
84
Mike Frysinger4b497472010-10-20 01:06:48 -040085static const MII_field_desc_t reg_2_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +000086 { 15, 0, 0xffff, "OUI portion" },
87};
88
Mike Frysinger4b497472010-10-20 01:06:48 -040089static const MII_field_desc_t reg_3_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +000090 { 15, 10, 0x3f, "OUI portion" },
91 { 9, 4, 0x3f, "manufacturer part number" },
92 { 3, 0, 0x0f, "manufacturer rev. number" },
93};
94
Mike Frysinger4b497472010-10-20 01:06:48 -040095static const MII_field_desc_t reg_4_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +000096 { 15, 15, 0x01, "next page able" },
97 { 14, 14, 0x01, "reserved" },
98 { 13, 13, 0x01, "remote fault" },
99 { 12, 12, 0x01, "reserved" },
100 { 11, 11, 0x01, "asymmetric pause" },
101 { 10, 10, 0x01, "pause enable" },
102 { 9, 9, 0x01, "100BASE-T4 able" },
103 { 8, 8, 0x01, "100BASE-TX full duplex able" },
104 { 7, 7, 0x01, "100BASE-TX able" },
105 { 6, 6, 0x01, "10BASE-T full duplex able" },
106 { 5, 5, 0x01, "10BASE-T able" },
107 { 4, 0, 0x1f, "xxx to do" },
108};
109
Mike Frysinger4b497472010-10-20 01:06:48 -0400110static const MII_field_desc_t reg_5_desc_tbl[] = {
wdenk61066ec2004-04-18 22:57:51 +0000111 { 15, 15, 0x01, "next page able" },
112 { 14, 14, 0x01, "acknowledge" },
113 { 13, 13, 0x01, "remote fault" },
114 { 12, 12, 0x01, "(reserved)" },
115 { 11, 11, 0x01, "asymmetric pause able" },
116 { 10, 10, 0x01, "pause able" },
117 { 9, 9, 0x01, "100BASE-T4 able" },
118 { 8, 8, 0x01, "100BASE-X full duplex able" },
119 { 7, 7, 0x01, "100BASE-TX able" },
120 { 6, 6, 0x01, "10BASE-T full duplex able" },
121 { 5, 5, 0x01, "10BASE-T able" },
122 { 4, 0, 0x1f, "xxx to do" },
123};
wdenk61066ec2004-04-18 22:57:51 +0000124typedef struct _MII_field_desc_and_len_t {
Mike Frysinger4b497472010-10-20 01:06:48 -0400125 const MII_field_desc_t *pdesc;
wdenk61066ec2004-04-18 22:57:51 +0000126 ushort len;
127} MII_field_desc_and_len_t;
128
Mike Frysinger4b497472010-10-20 01:06:48 -0400129static const MII_field_desc_and_len_t desc_and_len_tbl[] = {
130 { reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl) },
131 { reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl) },
132 { reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl) },
133 { reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl) },
134 { reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl) },
135 { reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl) },
wdenk61066ec2004-04-18 22:57:51 +0000136};
137
138static void dump_reg(
139 ushort regval,
Mike Frysinger4b497472010-10-20 01:06:48 -0400140 const MII_reg_desc_t *prd,
141 const MII_field_desc_and_len_t *pdl);
wdenk61066ec2004-04-18 22:57:51 +0000142
143static int special_field(
144 ushort regno,
Mike Frysinger4b497472010-10-20 01:06:48 -0400145 const MII_field_desc_t *pdesc,
wdenk61066ec2004-04-18 22:57:51 +0000146 ushort regval);
147
Mike Frysinger4b497472010-10-20 01:06:48 -0400148static void MII_dump_0_to_5(
wdenk61066ec2004-04-18 22:57:51 +0000149 ushort regvals[6],
150 uchar reglo,
151 uchar reghi)
152{
153 ulong i;
154
155 for (i = 0; i < 6; i++) {
156 if ((reglo <= i) && (i <= reghi))
157 dump_reg(regvals[i], &reg_0_5_desc_tbl[i],
158 &desc_and_len_tbl[i]);
159 }
160}
161
162static void dump_reg(
163 ushort regval,
Mike Frysinger4b497472010-10-20 01:06:48 -0400164 const MII_reg_desc_t *prd,
165 const MII_field_desc_and_len_t *pdl)
wdenk61066ec2004-04-18 22:57:51 +0000166{
167 ulong i;
168 ushort mask_in_place;
Mike Frysinger4b497472010-10-20 01:06:48 -0400169 const MII_field_desc_t *pdesc;
wdenk61066ec2004-04-18 22:57:51 +0000170
171 printf("%u. (%04hx) -- %s --\n",
172 prd->regno, regval, prd->name);
173
174 for (i = 0; i < pdl->len; i++) {
175 pdesc = &pdl->pdesc[i];
176
177 mask_in_place = pdesc->mask << pdesc->lo;
178
179 printf(" (%04hx:%04hx) %u.",
180 mask_in_place,
181 regval & mask_in_place,
182 prd->regno);
183
184 if (special_field(prd->regno, pdesc, regval)) {
185 }
186 else {
187 if (pdesc->hi == pdesc->lo)
188 printf("%2u ", pdesc->lo);
189 else
190 printf("%2u-%2u", pdesc->hi, pdesc->lo);
191 printf(" = %5u %s",
192 (regval & mask_in_place) >> pdesc->lo,
193 pdesc->name);
194 }
195 printf("\n");
196
197 }
198 printf("\n");
199}
200
201/* Special fields:
202** 0.6,13
203** 0.8
204** 2.15-0
205** 3.15-0
206** 4.4-0
207** 5.4-0
208*/
209
210static int special_field(
211 ushort regno,
Mike Frysinger4b497472010-10-20 01:06:48 -0400212 const MII_field_desc_t *pdesc,
wdenk61066ec2004-04-18 22:57:51 +0000213 ushort regval)
214{
215 if ((regno == 0) && (pdesc->lo == 6)) {
wdenk656140b2004-04-25 13:18:40 +0000216 ushort speed_bits = regval & PHY_BMCR_SPEED_MASK;
wdenk61066ec2004-04-18 22:57:51 +0000217 printf("%2u,%2u = b%u%u speed selection = %s Mbps",
218 6, 13,
219 (regval >> 6) & 1,
220 (regval >> 13) & 1,
wdenk656140b2004-04-25 13:18:40 +0000221 speed_bits == PHY_BMCR_1000_MBPS ? "1000" :
222 speed_bits == PHY_BMCR_100_MBPS ? "100" :
223 speed_bits == PHY_BMCR_10_MBPS ? "10" :
wdenk61066ec2004-04-18 22:57:51 +0000224 "???");
225 return 1;
226 }
227
228 else if ((regno == 0) && (pdesc->lo == 8)) {
229 printf("%2u = %5u duplex = %s",
230 pdesc->lo,
231 (regval >> pdesc->lo) & 1,
232 ((regval >> pdesc->lo) & 1) ? "full" : "half");
233 return 1;
234 }
235
236 else if ((regno == 4) && (pdesc->lo == 0)) {
237 ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
238 printf("%2u-%2u = %5u selector = %s",
239 pdesc->hi, pdesc->lo, sel_bits,
wdenk656140b2004-04-25 13:18:40 +0000240 sel_bits == PHY_ANLPAR_PSB_802_3 ?
wdenk61066ec2004-04-18 22:57:51 +0000241 "IEEE 802.3" :
wdenk656140b2004-04-25 13:18:40 +0000242 sel_bits == PHY_ANLPAR_PSB_802_9 ?
wdenk61066ec2004-04-18 22:57:51 +0000243 "IEEE 802.9 ISLAN-16T" :
244 "???");
245 return 1;
246 }
247
248 else if ((regno == 5) && (pdesc->lo == 0)) {
249 ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
250 printf("%2u-%2u = %u selector = %s",
251 pdesc->hi, pdesc->lo, sel_bits,
wdenk656140b2004-04-25 13:18:40 +0000252 sel_bits == PHY_ANLPAR_PSB_802_3 ?
wdenk61066ec2004-04-18 22:57:51 +0000253 "IEEE 802.3" :
wdenk656140b2004-04-25 13:18:40 +0000254 sel_bits == PHY_ANLPAR_PSB_802_9 ?
wdenk61066ec2004-04-18 22:57:51 +0000255 "IEEE 802.9 ISLAN-16T" :
256 "???");
257 return 1;
258 }
259
260 return 0;
261}
262
Mike Frysinger4b497472010-10-20 01:06:48 -0400263static char last_op[2];
264static uint last_data;
265static uint last_addr_lo;
266static uint last_addr_hi;
267static uint last_reg_lo;
268static uint last_reg_hi;
wdenk61066ec2004-04-18 22:57:51 +0000269
270static void extract_range(
271 char * input,
272 unsigned char * plo,
273 unsigned char * phi)
274{
275 char * end;
276 *plo = simple_strtoul(input, &end, 16);
277 if (*end == '-') {
278 end++;
279 *phi = simple_strtoul(end, NULL, 16);
280 }
281 else {
282 *phi = *plo;
283 }
284}
285
wdenk20c98a62004-04-23 20:32:05 +0000286/* ---------------------------------------------------------------- */
Mike Frysinger4b497472010-10-20 01:06:48 -0400287static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk61066ec2004-04-18 22:57:51 +0000288{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200289 char op[2];
wdenk61066ec2004-04-18 22:57:51 +0000290 unsigned char addrlo, addrhi, reglo, reghi;
Wolfgang Denkedb65482005-09-24 21:54:50 +0200291 unsigned char addr, reg;
wdenk61066ec2004-04-18 22:57:51 +0000292 unsigned short data;
293 int rcode = 0;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400294 const char *devname;
wdenk61066ec2004-04-18 22:57:51 +0000295
Wolfgang Denk3b683112010-07-17 01:06:04 +0200296 if (argc < 2)
297 return cmd_usage(cmdtp);
Shinya Kuribayashi9a631042007-12-27 15:39:54 +0900298
TsiChung Liewb3162452008-03-30 01:22:13 -0500299#if defined(CONFIG_MII_INIT)
wdenk61066ec2004-04-18 22:57:51 +0000300 mii_init ();
301#endif
302
303 /*
304 * We use the last specified parameters, unless new ones are
305 * entered.
306 */
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200307 op[0] = last_op[0];
308 op[1] = last_op[1];
wdenk61066ec2004-04-18 22:57:51 +0000309 addrlo = last_addr_lo;
310 addrhi = last_addr_hi;
311 reglo = last_reg_lo;
312 reghi = last_reg_hi;
313 data = last_data;
314
315 if ((flag & CMD_FLAG_REPEAT) == 0) {
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200316 op[0] = argv[1][0];
317 if (strlen(argv[1]) > 1)
318 op[1] = argv[1][1];
319 else
320 op[1] = '\0';
321
wdenk61066ec2004-04-18 22:57:51 +0000322 if (argc >= 3)
323 extract_range(argv[2], &addrlo, &addrhi);
324 if (argc >= 4)
325 extract_range(argv[3], &reglo, &reghi);
326 if (argc >= 5)
327 data = simple_strtoul (argv[4], NULL, 16);
328 }
329
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200330 /* use current device */
331 devname = miiphy_get_current_dev();
332
wdenk61066ec2004-04-18 22:57:51 +0000333 /*
334 * check info/read/write.
335 */
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200336 if (op[0] == 'i') {
wdenk61066ec2004-04-18 22:57:51 +0000337 unsigned char j, start, end;
338 unsigned int oui;
339 unsigned char model;
340 unsigned char rev;
341
342 /*
343 * Look for any and all PHYs. Valid addresses are 0..31.
344 */
345 if (argc >= 3) {
Wolfgang Denkedb65482005-09-24 21:54:50 +0200346 start = addrlo; end = addrhi;
wdenk61066ec2004-04-18 22:57:51 +0000347 } else {
Wolfgang Denkedb65482005-09-24 21:54:50 +0200348 start = 0; end = 31;
wdenk61066ec2004-04-18 22:57:51 +0000349 }
350
Wolfgang Denkedb65482005-09-24 21:54:50 +0200351 for (j = start; j <= end; j++) {
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200352 if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
wdenk61066ec2004-04-18 22:57:51 +0000353 printf("PHY 0x%02X: "
354 "OUI = 0x%04X, "
355 "Model = 0x%02X, "
356 "Rev = 0x%02X, "
Larry Johnson966a80b2007-11-01 08:46:50 -0500357 "%3dbase%s, %s\n",
wdenk61066ec2004-04-18 22:57:51 +0000358 j, oui, model, rev,
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200359 miiphy_speed (devname, j),
Larry Johnson966a80b2007-11-01 08:46:50 -0500360 miiphy_is_1000base_x (devname, j)
361 ? "X" : "T",
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200362 (miiphy_duplex (devname, j) == FULL)
363 ? "FDX" : "HDX");
wdenk61066ec2004-04-18 22:57:51 +0000364 }
365 }
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200366 } else if (op[0] == 'r') {
wdenk61066ec2004-04-18 22:57:51 +0000367 for (addr = addrlo; addr <= addrhi; addr++) {
368 for (reg = reglo; reg <= reghi; reg++) {
369 data = 0xffff;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200370 if (miiphy_read (devname, addr, reg, &data) != 0) {
wdenk61066ec2004-04-18 22:57:51 +0000371 printf(
372 "Error reading from the PHY addr=%02x reg=%02x\n",
373 addr, reg);
374 rcode = 1;
Wolfgang Denkedb65482005-09-24 21:54:50 +0200375 } else {
wdenk61066ec2004-04-18 22:57:51 +0000376 if ((addrlo != addrhi) || (reglo != reghi))
377 printf("addr=%02x reg=%02x data=",
378 (uint)addr, (uint)reg);
379 printf("%04X\n", data & 0x0000FFFF);
380 }
381 }
382 if ((addrlo != addrhi) && (reglo != reghi))
383 printf("\n");
384 }
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200385 } else if (op[0] == 'w') {
wdenk61066ec2004-04-18 22:57:51 +0000386 for (addr = addrlo; addr <= addrhi; addr++) {
387 for (reg = reglo; reg <= reghi; reg++) {
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200388 if (miiphy_write (devname, addr, reg, data) != 0) {
wdenk61066ec2004-04-18 22:57:51 +0000389 printf("Error writing to the PHY addr=%02x reg=%02x\n",
390 addr, reg);
391 rcode = 1;
392 }
393 }
394 }
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200395 } else if (strncmp(op, "du", 2) == 0) {
wdenk61066ec2004-04-18 22:57:51 +0000396 ushort regs[6];
397 int ok = 1;
398 if ((reglo > 5) || (reghi > 5)) {
399 printf(
400 "The MII dump command only formats the "
401 "standard MII registers, 0-5.\n");
402 return 1;
403 }
404 for (addr = addrlo; addr <= addrhi; addr++) {
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200405 for (reg = reglo; reg < reghi + 1; reg++) {
406 if (miiphy_read(devname, addr, reg, &regs[reg]) != 0) {
wdenk61066ec2004-04-18 22:57:51 +0000407 ok = 0;
408 printf(
409 "Error reading from the PHY addr=%02x reg=%02x\n",
410 addr, reg);
411 rcode = 1;
412 }
413 }
414 if (ok)
415 MII_dump_0_to_5(regs, reglo, reghi);
416 printf("\n");
417 }
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200418 } else if (strncmp(op, "de", 2) == 0) {
419 if (argc == 2)
420 miiphy_listdev ();
421 else
422 miiphy_set_current_dev (argv[2]);
wdenk61066ec2004-04-18 22:57:51 +0000423 } else {
Wolfgang Denk3b683112010-07-17 01:06:04 +0200424 return cmd_usage(cmdtp);
wdenk61066ec2004-04-18 22:57:51 +0000425 }
426
427 /*
428 * Save the parameters for repeats.
429 */
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200430 last_op[0] = op[0];
431 last_op[1] = op[1];
wdenk61066ec2004-04-18 22:57:51 +0000432 last_addr_lo = addrlo;
433 last_addr_hi = addrhi;
434 last_reg_lo = reglo;
435 last_reg_hi = reghi;
436 last_data = data;
437
438 return rcode;
439}
440
441/***************************************************/
442
443U_BOOT_CMD(
444 mii, 5, 1, do_mii,
Peter Tyserdfb72b82009-01-27 18:03:12 -0600445 "MII utility commands",
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200446 "device - list available devices\n"
447 "mii device <devname> - set current device\n"
448 "mii info <addr> - display MII PHY info\n"
449 "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
450 "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
451 "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200452 "Addr and/or reg may be ranges, e.g. 2-7."
wdenk61066ec2004-04-18 22:57:51 +0000453);