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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liu49912402014-11-24 17:11:56 +08002/* Copyright 2014 Freescale Semiconductor, Inc.
Shengzhou Liu49912402014-11-24 17:11:56 +08003 */
4
5#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07006#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -07007#include <console.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06008#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -07009#include <init.h>
Shengzhou Liu49912402014-11-24 17:11:56 +080010#include <malloc.h>
11#include <ns16550.h>
12#include <nand.h>
13#include <i2c.h>
14#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <spi_flash.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
tang yuantian8dc02f32014-12-17 15:42:54 +080018#include "../common/sleep.h"
Simon Glassdd8e2242016-09-24 18:20:10 -060019#include "../common/spl.h"
Shengzhou Liu49912402014-11-24 17:11:56 +080020
21DECLARE_GLOBAL_DATA_PTR;
22
23phys_size_t get_effective_memsize(void)
24{
25 return CONFIG_SYS_L3_SIZE;
26}
27
Shengzhou Liu796b33a2015-07-28 10:46:47 +080028#if defined(CONFIG_SPL_MMC_BOOT)
29#define GPIO1_SD_SEL 0x00020000
30int board_mmc_getcd(struct mmc *mmc)
31{
Tom Rinid5c3bf22022-10-28 20:27:12 -040032 ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
Shengzhou Liu796b33a2015-07-28 10:46:47 +080033 u32 val = in_be32(&pgpio->gpdat);
34
35 /* GPIO1_14, 0: eMMC, 1: SD */
36 val &= GPIO1_SD_SEL;
37
38 return val ? -1 : 1;
39}
40
41int board_mmc_getwp(struct mmc *mmc)
42{
Tom Rinid5c3bf22022-10-28 20:27:12 -040043 ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
Shengzhou Liu796b33a2015-07-28 10:46:47 +080044 u32 val = in_be32(&pgpio->gpdat);
45
46 val &= GPIO1_SD_SEL;
47
48 return val ? -1 : 0;
49}
50#endif
51
Shengzhou Liu49912402014-11-24 17:11:56 +080052void board_init_f(ulong bootflag)
53{
54 u32 plat_ratio, sys_clk, ccb_clk;
Tom Rinid5c3bf22022-10-28 20:27:12 -040055 ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
Shengzhou Liu49912402014-11-24 17:11:56 +080056
57 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
58 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
59
60 /* Update GD pointer */
61 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
62
63 console_init_f();
64
tang yuantian8dc02f32014-12-17 15:42:54 +080065#ifdef CONFIG_DEEP_SLEEP
66 /* disable the console if boot from deep sleep */
67 if (is_warm_boot())
68 fsl_dp_disable_console();
69#endif
70
Shengzhou Liu49912402014-11-24 17:11:56 +080071 /* initialize selected port with appropriate baud rate */
Tom Rini8c70baa2021-12-14 13:36:40 -050072 sys_clk = get_board_sys_clk();
Shengzhou Liu49912402014-11-24 17:11:56 +080073 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
74 ccb_clk = sys_clk * plat_ratio / 2;
75
Simon Glass2b923982020-12-22 19:30:19 -070076 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
Shengzhou Liu49912402014-11-24 17:11:56 +080077 ccb_clk / 16 / CONFIG_BAUDRATE);
78
79#if defined(CONFIG_SPL_MMC_BOOT)
80 puts("\nSD boot...\n");
81#elif defined(CONFIG_SPL_SPI_BOOT)
82 puts("\nSPI boot...\n");
83#elif defined(CONFIG_SPL_NAND_BOOT)
84 puts("\nNAND boot...\n");
85#endif
86
87 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
88}
89
90void board_init_r(gd_t *gd, ulong dest_addr)
91{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090092 struct bd_info *bd;
Shengzhou Liu49912402014-11-24 17:11:56 +080093
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090094 bd = (struct bd_info *)(gd + sizeof(gd_t));
95 memset(bd, 0, sizeof(struct bd_info));
Shengzhou Liu49912402014-11-24 17:11:56 +080096 gd->bd = bd;
Shengzhou Liu49912402014-11-24 17:11:56 +080097
Simon Glass302445a2017-01-23 13:31:22 -070098 arch_cpu_init();
Shengzhou Liu49912402014-11-24 17:11:56 +080099 get_clocks();
100 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
101 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -0400102 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Shengzhou Liu49912402014-11-24 17:11:56 +0800103
104#ifdef CONFIG_SPL_NAND_BOOT
105 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500106 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu49912402014-11-24 17:11:56 +0800107#endif
108#ifdef CONFIG_SPL_MMC_BOOT
109 mmc_initialize(bd);
110 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500111 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu49912402014-11-24 17:11:56 +0800112#endif
113#ifdef CONFIG_SPL_SPI_BOOT
Simon Glassdd8e2242016-09-24 18:20:10 -0600114 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500115 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu49912402014-11-24 17:11:56 +0800116#endif
117
Tom Rini5cd7ece2019-11-18 20:02:10 -0500118 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -0600119 gd->env_valid = ENV_VALID;
Shengzhou Liu49912402014-11-24 17:11:56 +0800120
121 i2c_init_all();
122
Simon Glassd35f3382017-04-06 12:47:05 -0600123 dram_init();
Shengzhou Liu49912402014-11-24 17:11:56 +0800124
125#ifdef CONFIG_SPL_MMC_BOOT
126 mmc_boot();
127#elif defined(CONFIG_SPL_SPI_BOOT)
Simon Glassdd8e2242016-09-24 18:20:10 -0600128 fsl_spi_boot();
Shengzhou Liu49912402014-11-24 17:11:56 +0800129#elif defined(CONFIG_SPL_NAND_BOOT)
130 nand_boot();
131#endif
132}