Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d5aa5058a0191c631027186ad9dda0322cefe5d8 / . / arch / arm / dts / imx8mm-verdin.dtsi
blob: eafa88d980b327776d326ccb88d75bb9c03f06a6 [file] [log] [blame]
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "dt-bindings/phy/phy-imx8-pcie.h"
7#include "dt-bindings/pwm/pwm.h"
8#include "imx8mm.dtsi"
9
10/ {
11 chosen {
12 stdout-path = &uart1;
13 };
14
15 aliases {
16 rtc0 = &rtc_i2c;
17 rtc1 = &snvs_rtc;
18 };
19
20 backlight: backlight {
21 compatible = "pwm-backlight";
22 brightness-levels = <0 45 63 88 119 158 203 255>;
23 default-brightness-level = <4>;
24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
28 power-supply = <&reg_3p3v>;
29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
31 status = "disabled";
32 };
33
34 /* Fixed clock dedicated to SPI CAN controller */
35 clk20m: oscillator {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <20000000>;
39 };
40
41 gpio-keys {
42 compatible = "gpio-keys";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpio_keys>;
45
46 wakeup {
47 debounce-interval = <10>;
48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
50 label = "Wake-Up";
51 linux,code = <KEY_WAKEUP>;
52 wakeup-source;
53 };
54 };
55
56 /* Carrier Board Supplies */
57 reg_1p8v: regulator-1p8v {
58 compatible = "regulator-fixed";
59 regulator-max-microvolt = <1800000>;
60 regulator-min-microvolt = <1800000>;
61 regulator-name = "+V1.8_SW";
62 };
63
64 reg_3p3v: regulator-3p3v {
65 compatible = "regulator-fixed";
66 regulator-max-microvolt = <3300000>;
67 regulator-min-microvolt = <3300000>;
68 regulator-name = "+V3.3_SW";
69 };
70
71 reg_5p0v: regulator-5p0v {
72 compatible = "regulator-fixed";
73 regulator-max-microvolt = <5000000>;
74 regulator-min-microvolt = <5000000>;
75 regulator-name = "+V5_SW";
76 };
77
78 /* Non PMIC On-module Supplies */
79 reg_ethphy: regulator-ethphy {
80 compatible = "regulator-fixed";
81 enable-active-high;
82 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
83 off-on-delay = <500000>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_reg_eth>;
86 regulator-boot-on;
87 regulator-max-microvolt = <3300000>;
88 regulator-min-microvolt = <3300000>;
89 regulator-name = "On-module +V3.3_ETH";
90 startup-delay-us = <200000>;
91 };
92
93 reg_usb_otg1_vbus: regulator-usb-otg1 {
94 compatible = "regulator-fixed";
95 enable-active-high;
96 /* Verdin USB_1_EN (SODIMM 155) */
97 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_reg_usb1_en>;
100 regulator-max-microvolt = <5000000>;
101 regulator-min-microvolt = <5000000>;
102 regulator-name = "USB_1_EN";
103 };
104
105 reg_usb_otg2_vbus: regulator-usb-otg2 {
106 compatible = "regulator-fixed";
107 enable-active-high;
108 /* Verdin USB_2_EN (SODIMM 185) */
109 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_reg_usb2_en>;
112 regulator-max-microvolt = <5000000>;
113 regulator-min-microvolt = <5000000>;
114 regulator-name = "USB_2_EN";
115 };
116
117 reg_usdhc2_vmmc: regulator-usdhc2 {
118 compatible = "regulator-fixed";
119 enable-active-high;
120 /* Verdin SD_1_PWR_EN (SODIMM 76) */
121 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
122 off-on-delay = <100000>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
125 regulator-max-microvolt = <3300000>;
126 regulator-min-microvolt = <3300000>;
127 regulator-name = "+V3.3_SD";
128 startup-delay-us = <2000>;
129 };
130
131 reserved-memory {
132 #address-cells = <2>;
133 #size-cells = <2>;
134 ranges;
135
136 /* Use the kernel configuration settings instead */
137 /delete-node/ linux,cma;
138 };
139};
140
141&A53_0 {
142 cpu-supply = <&reg_vdd_arm>;
143};
144
145&A53_1 {
146 cpu-supply = <&reg_vdd_arm>;
147};
148
149&A53_2 {
150 cpu-supply = <&reg_vdd_arm>;
151};
152
153&A53_3 {
154 cpu-supply = <&reg_vdd_arm>;
155};
156
157&ddrc {
158 operating-points-v2 = <&ddrc_opp_table>;
159
160 ddrc_opp_table: opp-table {
161 compatible = "operating-points-v2";
162
163 opp-25M {
164 opp-hz = /bits/ 64 <25000000>;
165 };
166
167 opp-100M {
168 opp-hz = /bits/ 64 <100000000>;
169 };
170
171 opp-750M {
172 opp-hz = /bits/ 64 <750000000>;
173 };
174 };
175};
176
177/* Verdin SPI_1 */
178&ecspi2 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_ecspi2>;
184};
185
186/* Verdin CAN_1 (On-module) */
187&ecspi3 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_ecspi3>;
193 status = "okay";
194
195 can1: can@0 {
196 compatible = "microchip,mcp251xfd";
197 clocks = <&clk20m>;
198 interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_can1_int>;
201 reg = <0>;
202 spi-max-frequency = <8500000>;
203 };
204};
205
206/* Verdin ETH_1 (On-module PHY) */
207&fec1 {
208 fsl,magic-packet;
209 phy-handle = <&ethphy0>;
210 phy-mode = "rgmii-id";
211 phy-supply = <&reg_ethphy>;
212 pinctrl-names = "default", "sleep";
213 pinctrl-0 = <&pinctrl_fec1>;
214 pinctrl-1 = <&pinctrl_fec1_sleep>;
215
216 mdio {
217 #address-cells = <1>;
218 #size-cells = <0>;
219
220 ethphy0: ethernet-phy@7 {
221 compatible = "ethernet-phy-ieee802.3-c22";
222 interrupt-parent = <&gpio1>;
223 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
224 micrel,led-mode = <0>;
225 reg = <7>;
226 };
227 };
228};
229
230/* Verdin QSPI_1 */
231&flexspi {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_flexspi0>;
234};
235
236&gpio1 {
237 gpio-line-names = "SODIMM_216",
238 "SODIMM_19",
239 "",
240 "",
241 "",
242 "",
243 "",
244 "",
245 "SODIMM_220",
246 "SODIMM_222",
247 "",
248 "SODIMM_218",
249 "SODIMM_155",
250 "SODIMM_157",
251 "SODIMM_185",
252 "SODIMM_187";
253};
254
255&gpio2 {
256 gpio-line-names = "",
257 "",
258 "",
259 "",
260 "",
261 "",
262 "",
263 "",
264 "",
265 "",
266 "",
267 "",
268 "SODIMM_84",
269 "SODIMM_78",
270 "SODIMM_74",
271 "SODIMM_80",
272 "SODIMM_82",
273 "SODIMM_70",
274 "SODIMM_72";
275};
276
277&gpio5 {
278 gpio-line-names = "SODIMM_131",
279 "",
280 "SODIMM_91",
281 "SODIMM_16",
282 "SODIMM_15",
283 "SODIMM_208",
284 "SODIMM_137",
285 "SODIMM_139",
286 "SODIMM_141",
287 "SODIMM_143",
288 "SODIMM_196",
289 "SODIMM_200",
290 "SODIMM_198",
291 "SODIMM_202",
292 "",
293 "",
294 "SODIMM_55",
295 "SODIMM_53",
296 "SODIMM_95",
297 "SODIMM_93",
298 "SODIMM_14",
299 "SODIMM_12",
300 "",
301 "",
302 "",
303 "",
304 "SODIMM_210",
305 "SODIMM_212",
306 "SODIMM_151",
307 "SODIMM_153";
308
309 ctrl-sleep-moci-hog {
310 gpio-hog;
311 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
312 gpios = <1 GPIO_ACTIVE_HIGH>;
313 line-name = "CTRL_SLEEP_MOCI#";
314 output-high;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
317 };
318};
319
320/* On-module I2C */
321&i2c1 {
322 clock-frequency = <400000>;
323 pinctrl-names = "default", "gpio";
324 pinctrl-0 = <&pinctrl_i2c1>;
325 pinctrl-1 = <&pinctrl_i2c1_gpio>;
326 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
327 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
328 status = "okay";
329
330 pca9450: pmic@25 {
331 compatible = "nxp,pca9450a";
332 interrupt-parent = <&gpio1>;
333 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
334 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_pmic>;
337 reg = <0x25>;
338 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
339
340 /*
341 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
342 * behind this PMIC.
343 */
344
345 regulators {
346 reg_vdd_soc: BUCK1 {
347 nxp,dvs-run-voltage = <850000>;
348 nxp,dvs-standby-voltage = <800000>;
349 regulator-always-on;
350 regulator-boot-on;
351 regulator-max-microvolt = <850000>;
352 regulator-min-microvolt = <800000>;
353 regulator-name = "On-module +VDD_SOC (BUCK1)";
354 regulator-ramp-delay = <3125>;
355 };
356
357 reg_vdd_arm: BUCK2 {
358 nxp,dvs-run-voltage = <950000>;
359 nxp,dvs-standby-voltage = <850000>;
360 regulator-always-on;
361 regulator-boot-on;
362 regulator-max-microvolt = <950000>;
363 regulator-min-microvolt = <850000>;
364 regulator-name = "On-module +VDD_ARM (BUCK2)";
365 regulator-ramp-delay = <3125>;
366 };
367
368 reg_vdd_dram: BUCK3 {
369 regulator-always-on;
370 regulator-boot-on;
371 regulator-max-microvolt = <950000>;
372 regulator-min-microvolt = <850000>;
373 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
374 };
375
376 reg_vdd_3v3: BUCK4 {
377 regulator-always-on;
378 regulator-boot-on;
379 regulator-max-microvolt = <3300000>;
380 regulator-min-microvolt = <3300000>;
381 regulator-name = "On-module +V3.3 (BUCK4)";
382 };
383
384 reg_vdd_1v8: BUCK5 {
385 regulator-always-on;
386 regulator-boot-on;
387 regulator-max-microvolt = <1800000>;
388 regulator-min-microvolt = <1800000>;
389 regulator-name = "PWR_1V8_MOCI (BUCK5)";
390 };
391
392 reg_nvcc_dram: BUCK6 {
393 regulator-always-on;
394 regulator-boot-on;
395 regulator-max-microvolt = <1100000>;
396 regulator-min-microvolt = <1100000>;
397 regulator-name = "On-module +VDD_DDR (BUCK6)";
398 };
399
400 reg_nvcc_snvs: LDO1 {
401 regulator-always-on;
402 regulator-boot-on;
403 regulator-max-microvolt = <1800000>;
404 regulator-min-microvolt = <1800000>;
405 regulator-name = "On-module +V1.8_SNVS (LDO1)";
406 };
407
408 reg_vdd_snvs: LDO2 {
409 regulator-always-on;
410 regulator-boot-on;
411 regulator-max-microvolt = <900000>;
412 regulator-min-microvolt = <800000>;
413 regulator-name = "On-module +V0.8_SNVS (LDO2)";
414 };
415
416 reg_vdda: LDO3 {
417 regulator-always-on;
418 regulator-boot-on;
419 regulator-max-microvolt = <1800000>;
420 regulator-min-microvolt = <1800000>;
421 regulator-name = "On-module +V1.8A (LDO3)";
422 };
423
424 reg_vdd_phy: LDO4 {
425 regulator-always-on;
426 regulator-boot-on;
427 regulator-max-microvolt = <900000>;
428 regulator-min-microvolt = <900000>;
429 regulator-name = "On-module +V0.9_MIPI (LDO4)";
430 };
431
432 reg_nvcc_sd: LDO5 {
433 regulator-max-microvolt = <3300000>;
434 regulator-min-microvolt = <1800000>;
435 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
436 };
437 };
438 };
439
440 rtc_i2c: rtc@32 {
441 compatible = "epson,rx8130";
442 reg = <0x32>;
443 };
444
445 adc@49 {
446 compatible = "ti,ads1015";
447 reg = <0x49>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450
451 /* Verdin I2C_1 (ADC_4 - ADC_3) */
452 channel@0 {
453 reg = <0>;
454 ti,datarate = <4>;
455 ti,gain = <2>;
456 };
457
458 /* Verdin I2C_1 (ADC_4 - ADC_1) */
459 channel@1 {
460 reg = <1>;
461 ti,datarate = <4>;
462 ti,gain = <2>;
463 };
464
465 /* Verdin I2C_1 (ADC_3 - ADC_1) */
466 channel@2 {
467 reg = <2>;
468 ti,datarate = <4>;
469 ti,gain = <2>;
470 };
471
472 /* Verdin I2C_1 (ADC_2 - ADC_1) */
473 channel@3 {
474 reg = <3>;
475 ti,datarate = <4>;
476 ti,gain = <2>;
477 };
478
479 /* Verdin I2C_1 ADC_4 */
480 channel@4 {
481 reg = <4>;
482 ti,datarate = <4>;
483 ti,gain = <2>;
484 };
485
486 /* Verdin I2C_1 ADC_3 */
487 channel@5 {
488 reg = <5>;
489 ti,datarate = <4>;
490 ti,gain = <2>;
491 };
492
493 /* Verdin I2C_1 ADC_2 */
494 channel@6 {
495 reg = <6>;
496 ti,datarate = <4>;
497 ti,gain = <2>;
498 };
499
500 /* Verdin I2C_1 ADC_1 */
501 channel@7 {
502 reg = <7>;
503 ti,datarate = <4>;
504 ti,gain = <2>;
505 };
506 };
507
508 eeprom@50 {
509 compatible = "st,24c02";
510 pagesize = <16>;
511 reg = <0x50>;
512 };
513};
514
515/* Verdin I2C_2_DSI */
516&i2c2 {
517 clock-frequency = <10000>;
518 pinctrl-names = "default", "gpio";
519 pinctrl-0 = <&pinctrl_i2c2>;
520 pinctrl-1 = <&pinctrl_i2c2_gpio>;
521 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
522 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
523 status = "disabled";
524};
525
526/* Verdin I2C_3_HDMI N/A */
527
528/* Verdin I2C_4_CSI */
529&i2c3 {
530 clock-frequency = <400000>;
531 pinctrl-names = "default", "gpio";
532 pinctrl-0 = <&pinctrl_i2c3>;
533 pinctrl-1 = <&pinctrl_i2c3_gpio>;
534 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
535 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
536};
537
538/* Verdin I2C_1 */
539&i2c4 {
540 clock-frequency = <400000>;
541 pinctrl-names = "default", "gpio";
542 pinctrl-0 = <&pinctrl_i2c4>;
543 pinctrl-1 = <&pinctrl_i2c4_gpio>;
544 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
545 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
546
547 gpio_expander_21: gpio-expander@21 {
548 compatible = "nxp,pcal6416";
549 #gpio-cells = <2>;
550 gpio-controller;
551 reg = <0x21>;
552 vcc-supply = <&reg_3p3v>;
553 status = "disabled";
554 };
555
556 lvds_ti_sn65dsi83: bridge@2c {
557 compatible = "ti,sn65dsi83";
558 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
559 /* Verdin GPIO_10_DSI (SODIMM 21) */
560 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
563 reg = <0x2c>;
564 status = "disabled";
565 };
566
567 /* Current measurement into module VCC */
568 hwmon: hwmon@40 {
569 compatible = "ti,ina219";
570 reg = <0x40>;
571 shunt-resistor = <10000>;
572 status = "disabled";
573 };
574
575 hdmi_lontium_lt8912: hdmi@48 {
576 compatible = "lontium,lt8912b";
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
579 reg = <0x48>;
580 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
581 /* Verdin GPIO_10_DSI (SODIMM 21) */
582 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
583 status = "disabled";
584 };
585
586 atmel_mxt_ts: touch@4a {
587 compatible = "atmel,maxtouch";
588 /*
589 * Verdin GPIO_9_DSI
590 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
591 */
592 interrupt-parent = <&gpio3>;
593 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
596 reg = <0x4a>;
597 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
598 reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
599 status = "disabled";
600 };
601
602 /* Temperature sensor on carrier board */
603 hwmon_temp: sensor@4f {
604 compatible = "ti,tmp75c";
605 reg = <0x4f>;
606 status = "disabled";
607 };
608
609 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
610 eeprom_display_adapter: eeprom@50 {
611 compatible = "st,24c02";
612 pagesize = <16>;
613 reg = <0x50>;
614 status = "disabled";
615 };
616
617 /* EEPROM on carrier board */
618 eeprom_carrier_board: eeprom@57 {
619 compatible = "st,24c02";
620 pagesize = <16>;
621 reg = <0x57>;
622 status = "disabled";
623 };
624};
625
626/* Verdin PCIE_1 */
627&pcie0 {
628 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
629 <&clk IMX8MM_CLK_PCIE1_CTRL>;
630 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
631 <&clk IMX8MM_SYS_PLL2_250M>;
632 assigned-clock-rates = <10000000>, <250000000>;
633 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
634 <&clk IMX8MM_CLK_PCIE1_PHY>;
635 clock-names = "pcie", "pcie_aux", "pcie_bus";
636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_pcie0>;
638 /* PCIE_1_RESET# (SODIMM 244) */
639 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
640};
641
642&pcie_phy {
643 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
644 fsl,clkreq-unsupported;
645 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
646 fsl,tx-deemph-gen1 = <0x2d>;
647 fsl,tx-deemph-gen2 = <0xf>;
648};
649
650/* Verdin PWM_3_DSI */
651&pwm1 {
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_pwm_1>;
654 #pwm-cells = <3>;
655};
656
657/* Verdin PWM_1 */
658&pwm2 {
659 pinctrl-names = "default";
660 pinctrl-0 = <&pinctrl_pwm_2>;
661 #pwm-cells = <3>;
662};
663
664/* Verdin PWM_2 */
665&pwm3 {
666 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_pwm_3>;
668 #pwm-cells = <3>;
669};
670
671/* Verdin I2S_1 */
672&sai2 {
673 #sound-dai-cells = <0>;
674 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
675 assigned-clock-rates = <24576000>;
676 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_sai2>;
679};
680
681&snvs_pwrkey {
682 status = "okay";
683};
684
685/* Verdin UART_3, used as the Linux console */
686&uart1 {
687 pinctrl-names = "default";
688 pinctrl-0 = <&pinctrl_uart1>;
689};
690
691/* Verdin UART_1 */
692&uart2 {
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_uart2>;
695 uart-has-rtscts;
696};
697
698/* Verdin UART_2 */
699&uart3 {
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_uart3>;
702 uart-has-rtscts;
703};
704
705/*
706 * Verdin UART_4
707 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
708 */
709&uart4 {
710 pinctrl-names = "default";
711 pinctrl-0 = <&pinctrl_uart4>;
712};
713
714/* Verdin USB_1 */
715&usbotg1 {
716 adp-disable;
717 dr_mode = "otg";
718 hnp-disable;
719 over-current-active-low;
720 samsung,picophy-dc-vol-level-adjust = <7>;
721 samsung,picophy-pre-emp-curr-control = <3>;
722 srp-disable;
723 vbus-supply = <&reg_usb_otg1_vbus>;
724};
725
726/* Verdin USB_2 */
727&usbotg2 {
728 dr_mode = "host";
729 over-current-active-low;
730 samsung,picophy-dc-vol-level-adjust = <7>;
731 samsung,picophy-pre-emp-curr-control = <3>;
732 vbus-supply = <&reg_usb_otg2_vbus>;
733};
734
735&usbphynop1 {
736 vcc-supply = <&reg_vdd_3v3>;
737};
738
739&usbphynop2 {
740 vcc-supply = <&reg_vdd_3v3>;
741};
742
743/* On-module eMMC */
744&usdhc1 {
745 bus-width = <8>;
746 keep-power-in-suspend;
747 non-removable;
748 pinctrl-names = "default", "state_100mhz", "state_200mhz";
749 pinctrl-0 = <&pinctrl_usdhc1>;
750 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
751 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
752 status = "okay";
753};
754
755/* Verdin SD_1 */
756&usdhc2 {
757 bus-width = <4>;
758 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
759 disable-wp;
760 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
761 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
762 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
763 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
764 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
765 vmmc-supply = <&reg_usdhc2_vmmc>;
766};
767
768&wdog1 {
769 fsl,ext-reset-output;
770 pinctrl-names = "default";
771 pinctrl-0 = <&pinctrl_wdog>;
772 status = "okay";
773};
774
775&iomuxc {
776 pinctrl-names = "default";
777 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
778 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
779 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
780 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
781 <&pinctrl_pmic_tpm_ena>;
782
783 pinctrl_can1_int: can1intgrp {
784 fsl,pins =
785 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
786 };
787
788 pinctrl_can2_int: can2intgrp {
789 fsl,pins =
790 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
791 };
792
793 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
794 fsl,pins =
795 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
796 };
797
798 pinctrl_ecspi2: ecspi2grp {
799 fsl,pins =
800 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
801 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
802 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
803 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
804 };
805
806 pinctrl_ecspi3: ecspi3grp {
807 fsl,pins =
808 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
809 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
810 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
811 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
812 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
813 };
814
815 pinctrl_fec1: fec1grp {
816 fsl,pins =
817 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
818 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
819 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
820 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
821 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
822 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
823 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
824 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
825 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
826 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
827 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
828 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
829 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
830 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
831 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
832 };
833
834 pinctrl_fec1_sleep: fec1-sleepgrp {
835 fsl,pins =
836 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
837 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
838 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
839 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
840 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
841 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
842 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
843 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
844 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
845 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
846 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
847 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
848 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
849 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
850 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
851 };
852
853 pinctrl_flexspi0: flexspi0grp {
854 fsl,pins =
855 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
856 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
857 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
858 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
859 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
860 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
861 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
862 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
863 };
864
865 pinctrl_gpio1: gpio1grp {
866 fsl,pins =
867 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
868 };
869
870 pinctrl_gpio2: gpio2grp {
871 fsl,pins =
872 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
873 };
874
875 pinctrl_gpio3: gpio3grp {
876 fsl,pins =
877 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
878 };
879
880 pinctrl_gpio4: gpio4grp {
881 fsl,pins =
882 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
883 };
884
885 pinctrl_gpio5: gpio5grp {
886 fsl,pins =
887 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
888 };
889
890 pinctrl_gpio6: gpio6grp {
891 fsl,pins =
892 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
893 };
894
895 pinctrl_gpio7: gpio7grp {
896 fsl,pins =
897 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
898 };
899
900 pinctrl_gpio8: gpio8grp {
901 fsl,pins =
902 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
903 };
904
905 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
906 pinctrl_gpio_9_dsi: gpio9dsigrp {
907 fsl,pins =
908 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
909 };
910
911 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
912 pinctrl_gpio_10_dsi: gpio10dsigrp {
913 fsl,pins =
914 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
915 };
916
917 pinctrl_gpio_hog1: gpiohog1grp {
918 fsl,pins =
919 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
920 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
921 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
922 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
923 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
924 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
925 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
926 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
927 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
928 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
929 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
930 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
931 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
932 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
933 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
934 };
935
936 pinctrl_gpio_hog2: gpiohog2grp {
937 fsl,pins =
938 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
939 };
940
941 pinctrl_gpio_hog3: gpiohog3grp {
942 fsl,pins =
943 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
944 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
945 };
946
947 pinctrl_gpio_keys: gpiokeysgrp {
948 fsl,pins =
949 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
950 };
951
952 /* On-module I2C */
953 pinctrl_i2c1: i2c1grp {
954 fsl,pins =
955 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
956 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
957 };
958
959 pinctrl_i2c1_gpio: i2c1gpiogrp {
960 fsl,pins =
961 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
962 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
963 };
964
965 /* Verdin I2C_4_CSI */
966 pinctrl_i2c2: i2c2grp {
967 fsl,pins =
968 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
969 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
970 };
971
972 pinctrl_i2c2_gpio: i2c2gpiogrp {
973 fsl,pins =
974 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
975 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
976 };
977
978 /* Verdin I2C_2_DSI */
979 pinctrl_i2c3: i2c3grp {
980 fsl,pins =
981 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
982 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
983 };
984
985 pinctrl_i2c3_gpio: i2c3gpiogrp {
986 fsl,pins =
987 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
988 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
989 };
990
991 /* Verdin I2C_1 */
992 pinctrl_i2c4: i2c4grp {
993 fsl,pins =
994 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
995 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
996 };
997
998 pinctrl_i2c4_gpio: i2c4gpiogrp {
999 fsl,pins =
1000 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1001 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1002 };
1003
1004 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1005 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1006 fsl,pins =
1007 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1008 };
1009
1010 /* Verdin I2S_2_D_OUT shared with SAI5 */
1011 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1012 fsl,pins =
1013 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1014 };
1015
1016 pinctrl_pcie0: pcie0grp {
1017 fsl,pins =
1018 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1019 /* PMIC_EN_PCIe_CLK, unused */
1020 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1021 };
1022
1023 pinctrl_pmic: pmicirqgrp {
1024 fsl,pins =
1025 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1026 };
1027
1028 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1029 pinctrl_pwm_1: pwm1grp {
1030 fsl,pins =
1031 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1032 };
1033
1034 pinctrl_pwm_2: pwm2grp {
1035 fsl,pins =
1036 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1037 };
1038
1039 pinctrl_pwm_3: pwm3grp {
1040 fsl,pins =
1041 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1042 };
1043
1044 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1045 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1046 fsl,pins =
1047 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1048 };
1049
1050 pinctrl_reg_eth: regethgrp {
1051 fsl,pins =
1052 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1053 };
1054
1055 pinctrl_reg_usb1_en: regusb1engrp {
1056 fsl,pins =
1057 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1058 };
1059
1060 pinctrl_reg_usb2_en: regusb2engrp {
1061 fsl,pins =
1062 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1063 };
1064
1065 pinctrl_sai2: sai2grp {
1066 fsl,pins =
1067 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1068 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1069 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1070 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1071 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1072 };
1073
1074 pinctrl_sai5: sai5grp {
1075 fsl,pins =
1076 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1077 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1078 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1079 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1080 };
1081
1082 /* control signal for optional ATTPM20P or SE050 */
1083 pinctrl_pmic_tpm_ena: pmictpmenagrp {
1084 fsl,pins =
1085 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1086 };
1087
1088 pinctrl_tsp: tspgrp {
1089 fsl,pins =
1090 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1091 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1092 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1093 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1094 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1095 };
1096
1097 pinctrl_uart1: uart1grp {
1098 fsl,pins =
1099 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1100 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1101 };
1102
1103 pinctrl_uart2: uart2grp {
1104 fsl,pins =
1105 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1106 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1107 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1108 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1109 };
1110
1111 pinctrl_uart3: uart3grp {
1112 fsl,pins =
1113 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1114 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1115 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1116 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1117 };
1118
1119 pinctrl_uart4: uart4grp {
1120 fsl,pins =
1121 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1122 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1123 };
1124
1125 pinctrl_usdhc1: usdhc1grp {
1126 fsl,pins =
1127 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1128 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1129 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1130 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1131 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1132 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1133 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1134 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1135 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1136 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1137 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1138 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1139 };
1140
1141 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1142 fsl,pins =
1143 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1144 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1145 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1146 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1147 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1148 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1149 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1150 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1151 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1152 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1153 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1154 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1155 };
1156
1157 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1158 fsl,pins =
1159 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1160 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1161 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1162 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1163 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1164 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1165 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1166 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1167 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1168 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1169 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1170 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1171 };
1172
1173 pinctrl_usdhc2_cd: usdhc2cdgrp {
1174 fsl,pins =
1175 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1176 };
1177
1178 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1179 fsl,pins =
1180 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1181 };
1182
1183 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1184 fsl,pins =
1185 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1186 };
1187
1188 /*
1189 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1190 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1191 */
1192 pinctrl_usdhc2: usdhc2grp {
1193 fsl,pins =
1194 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1195 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1196 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1197 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1198 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1199 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1200 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1201 };
1202
1203 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1204 fsl,pins =
1205 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1206 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1207 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1208 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1209 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1210 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1211 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1212 };
1213
1214 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1215 fsl,pins =
1216 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1217 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1218 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1219 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1220 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1221 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1222 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1223 };
1224
1225 /* Avoid backfeeding with removed card power */
1226 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1227 fsl,pins =
1228 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1229 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1230 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1231 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1232 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1233 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1234 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1235 };
1236
1237 /*
1238 * On-module Wi-Fi/BT or type specific SDHC interface
1239 * (e.g. on X52 extension slot of Verdin Development Board)
1240 */
1241 pinctrl_usdhc3: usdhc3grp {
1242 fsl,pins =
1243 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1244 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1245 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1246 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1247 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1248 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1249 };
1250
1251 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1252 fsl,pins =
1253 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1254 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1255 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1256 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1257 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1258 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1259 };
1260
1261 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1262 fsl,pins =
1263 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1264 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1265 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1266 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1267 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1268 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1269 };
1270
1271 pinctrl_wdog: wdoggrp {
1272 fsl,pins =
1273 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1274 };
1275
1276 pinctrl_wifi_ctrl: wifictrlgrp {
1277 fsl,pins =
1278 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1279 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1280 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1281 };
1282
1283 pinctrl_wifi_i2s: bti2sgrp {
1284 fsl,pins =
1285 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1286 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1287 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1288 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1289 };
1290
1291 pinctrl_wifi_pwr_en: wifipwrengrp {
1292 fsl,pins =
1293 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1294 };
1295};