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Bo Shen58258bd2014-11-10 15:46:22 +08001/*
2 * Copyright (C) 2014 Atmel
3 * Bo Shen <voice.shen@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/at91_common.h>
Bo Shen58258bd2014-11-10 15:46:22 +080011#include <asm/arch/at91_rstc.h>
Bo Shene47c0072014-12-15 13:24:39 +080012#include <asm/arch/atmel_mpddrc.h>
Bo Shen47d205d2014-12-03 18:02:22 +080013#include <asm/arch/atmel_usba_udc.h>
Bo Shen58258bd2014-11-10 15:46:22 +080014#include <asm/arch/gpio.h>
15#include <asm/arch/clk.h>
16#include <asm/arch/sama5d3_smc.h>
17#include <asm/arch/sama5d4.h>
Bo Shen0a3c2fc2015-01-08 15:20:11 +080018#include <atmel_hlcdc.h>
Bo Shen58258bd2014-11-10 15:46:22 +080019#include <atmel_mci.h>
20#include <lcd.h>
21#include <mmc.h>
22#include <net.h>
23#include <netdev.h>
24#include <nand.h>
25#include <spi.h>
Wu, Josh1d55b502015-02-04 11:03:32 +080026#include <version.h>
Bo Shen58258bd2014-11-10 15:46:22 +080027
28DECLARE_GLOBAL_DATA_PTR;
29
30#ifdef CONFIG_ATMEL_SPI
Wenyou Yang3143ac22017-04-13 10:31:16 +080031#ifndef CONFIG_DM_SPI
Bo Shen58258bd2014-11-10 15:46:22 +080032int spi_cs_is_valid(unsigned int bus, unsigned int cs)
33{
34 return bus == 0 && cs == 0;
35}
Wenyou Yang3143ac22017-04-13 10:31:16 +080036#endif
Bo Shen58258bd2014-11-10 15:46:22 +080037
38void spi_cs_activate(struct spi_slave *slave)
39{
40 at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
41}
42
43void spi_cs_deactivate(struct spi_slave *slave)
44{
45 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
46}
47
48static void sama5d4_xplained_spi0_hw_init(void)
49{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +080050 at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
Bo Shen58258bd2014-11-10 15:46:22 +080053
54 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
55
56 /* Enable clock */
57 at91_periph_clk_enable(ATMEL_ID_SPI0);
58}
59#endif /* CONFIG_ATMEL_SPI */
60
61#ifdef CONFIG_NAND_ATMEL
62static void sama5d4_xplained_nand_hw_init(void)
63{
64 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
65
66 at91_periph_clk_enable(ATMEL_ID_SMC);
67
68 /* Configure SMC CS3 for NAND */
69 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
70 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
71 &smc->cs[3].setup);
72 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
73 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
74 &smc->cs[3].pulse);
75 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
76 &smc->cs[3].cycle);
77 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
78 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
79 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
80 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
81 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
82 AT91_SMC_MODE_EXNW_DISABLE |
83 AT91_SMC_MODE_DBW_8 |
84 AT91_SMC_MODE_TDF_CYCLE(3),
85 &smc->cs[3].mode);
86
Wenyou Yang4a92a3e2017-03-23 12:44:36 +080087 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
88 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
89 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
90 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
91 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
92 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
93 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
94 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
95 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
96 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
97 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
98 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
99 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
100 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
Bo Shen58258bd2014-11-10 15:46:22 +0800101}
102#endif
103
104#ifdef CONFIG_CMD_USB
105static void sama5d4_xplained_usb_hw_init(void)
106{
107 at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
108 at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
109}
110#endif
111
112#ifdef CONFIG_LCD
113vidinfo_t panel_info = {
114 .vl_col = 480,
115 .vl_row = 272,
Bo Shen0a3c2fc2015-01-08 15:20:11 +0800116 .vl_clk = 9000000,
Bo Shen58258bd2014-11-10 15:46:22 +0800117 .vl_bpix = LCD_BPP,
Bo Shen58258bd2014-11-10 15:46:22 +0800118 .vl_tft = 1,
119 .vl_hsync_len = 41,
120 .vl_left_margin = 2,
121 .vl_right_margin = 2,
122 .vl_vsync_len = 11,
123 .vl_upper_margin = 2,
124 .vl_lower_margin = 2,
125 .mmio = ATMEL_BASE_LCDC,
126};
127
128/* No power up/down pin for the LCD pannel */
129void lcd_enable(void) { /* Empty! */ }
130void lcd_disable(void) { /* Empty! */ }
131
132unsigned int has_lcdc(void)
133{
134 return 1;
135}
136
137static void sama5d4_xplained_lcd_hw_init(void)
138{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800139 at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
140 at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
141 at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
142 at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
143 at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
144 at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
Bo Shen58258bd2014-11-10 15:46:22 +0800145
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800146 at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
147 at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
148 at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
149 at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
150 at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
151 at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
152 at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
153 at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
Bo Shen58258bd2014-11-10 15:46:22 +0800154
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800155 at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
156 at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
157 at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
158 at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
159 at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
160 at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
161 at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
162 at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
Bo Shen58258bd2014-11-10 15:46:22 +0800163
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800164 at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
165 at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
166 at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
167 at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
168 at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
169 at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
170 at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
171 at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
Bo Shen58258bd2014-11-10 15:46:22 +0800172
173 /* Enable clock */
174 at91_periph_clk_enable(ATMEL_ID_LCDC);
175}
176
177#ifdef CONFIG_LCD_INFO
178void lcd_show_board_info(void)
179{
180 ulong dram_size, nand_size;
181 int i;
182 char temp[32];
183
Wu, Josh1d55b502015-02-04 11:03:32 +0800184 lcd_printf("%s\n", U_BOOT_VERSION);
Bo Shen58258bd2014-11-10 15:46:22 +0800185 lcd_printf("2014 ATMEL Corp\n");
186 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
187 strmhz(temp, get_cpu_clk_rate()));
188
189 dram_size = 0;
190 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
191 dram_size += gd->bd->bi_dram[i].size;
192
193 nand_size = 0;
194#ifdef CONFIG_NAND_ATMEL
195 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
Scott Wood2c1b7e12016-05-30 13:57:55 -0500196 nand_size += nand_info[i]->size;
Bo Shen58258bd2014-11-10 15:46:22 +0800197#endif
198 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
199 dram_size >> 20, nand_size >> 20);
200}
201#endif /* CONFIG_LCD_INFO */
202
203#endif /* CONFIG_LCD */
204
205#ifdef CONFIG_GENERIC_ATMEL_MCI
206void sama5d4_xplained_mci1_hw_init(void)
207{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800208 at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
209 at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
210 at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
211 at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
212 at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
213 at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
Bo Shen58258bd2014-11-10 15:46:22 +0800214
215 /*
216 * As the mci io internal pull down is too strong, so if the io needs
217 * external pull up, the pull up resistor will be very small, if so
218 * the power consumption will increase, so disable the interanl pull
219 * down to save the power.
220 */
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800221 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
222 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
223 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
224 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
225 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
226 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
Bo Shen58258bd2014-11-10 15:46:22 +0800227
228 /* Enable clock */
229 at91_periph_clk_enable(ATMEL_ID_MCI1);
230}
231
232int board_mmc_init(bd_t *bis)
233{
Bo Shen09081732015-02-13 15:53:18 +0800234 /* Enable the power supply */
235 at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
236
Bo Shen58258bd2014-11-10 15:46:22 +0800237 return atmel_mci_init((void *)ATMEL_BASE_MCI1);
238}
239#endif /* CONFIG_GENERIC_ATMEL_MCI */
240
241#ifdef CONFIG_MACB
242void sama5d4_xplained_macb0_hw_init(void)
243{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800244 at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
245 at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
246 at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
247 at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
248 at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
249 at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
250 at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
251 at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
252 at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
253 at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
Bo Shen58258bd2014-11-10 15:46:22 +0800254
255 /* Enable clock */
256 at91_periph_clk_enable(ATMEL_ID_GMAC0);
257}
258#endif
259
260static void sama5d4_xplained_serial3_hw_init(void)
261{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800262 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
263 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
Bo Shen58258bd2014-11-10 15:46:22 +0800264
265 /* Enable clock */
266 at91_periph_clk_enable(ATMEL_ID_USART3);
267}
268
269int board_early_init_f(void)
270{
271 at91_periph_clk_enable(ATMEL_ID_PIOA);
272 at91_periph_clk_enable(ATMEL_ID_PIOB);
273 at91_periph_clk_enable(ATMEL_ID_PIOC);
274 at91_periph_clk_enable(ATMEL_ID_PIOD);
275 at91_periph_clk_enable(ATMEL_ID_PIOE);
276
277 sama5d4_xplained_serial3_hw_init();
278
279 return 0;
280}
281
282int board_init(void)
283{
284 /* adress of boot parameters */
285 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
286
287#ifdef CONFIG_ATMEL_SPI
288 sama5d4_xplained_spi0_hw_init();
289#endif
290#ifdef CONFIG_NAND_ATMEL
291 sama5d4_xplained_nand_hw_init();
292#endif
293#ifdef CONFIG_GENERIC_ATMEL_MCI
294 sama5d4_xplained_mci1_hw_init();
295#endif
296#ifdef CONFIG_MACB
297 sama5d4_xplained_macb0_hw_init();
298#endif
299#ifdef CONFIG_LCD
300 sama5d4_xplained_lcd_hw_init();
301#endif
302#ifdef CONFIG_CMD_USB
303 sama5d4_xplained_usb_hw_init();
304#endif
Bo Shen47d205d2014-12-03 18:02:22 +0800305#ifdef CONFIG_USB_GADGET_ATMEL_USBA
306 at91_udp_hw_init();
307#endif
Bo Shen58258bd2014-11-10 15:46:22 +0800308
309 return 0;
310}
311
312int dram_init(void)
313{
314 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
315 CONFIG_SYS_SDRAM_SIZE);
316 return 0;
317}
318
319int board_eth_init(bd_t *bis)
320{
321 int rc = 0;
322
323#ifdef CONFIG_MACB
324 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
325#endif
326
Bo Shen47d205d2014-12-03 18:02:22 +0800327#ifdef CONFIG_USB_GADGET_ATMEL_USBA
328 usba_udc_probe(&pdata);
329#ifdef CONFIG_USB_ETH_RNDIS
330 usb_eth_initialize(bis);
331#endif
332#endif
333
Bo Shen58258bd2014-11-10 15:46:22 +0800334 return rc;
335}
Bo Shene47c0072014-12-15 13:24:39 +0800336
337/* SPL */
338#ifdef CONFIG_SPL_BUILD
339void spl_board_init(void)
340{
341#ifdef CONFIG_SYS_USE_MMC
342 sama5d4_xplained_mci1_hw_init();
343#elif CONFIG_SYS_USE_NANDFLASH
344 sama5d4_xplained_nand_hw_init();
345#elif CONFIG_SYS_USE_SERIALFLASH
346 sama5d4_xplained_spi0_hw_init();
347#endif
348}
349
Wenyou Yangaa0a58d2016-02-01 18:12:15 +0800350static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
Bo Shene47c0072014-12-15 13:24:39 +0800351{
352 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
353
354 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
355 ATMEL_MPDDRC_CR_NR_ROW_14 |
356 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
357 ATMEL_MPDDRC_CR_NB_8BANKS |
358 ATMEL_MPDDRC_CR_NDQS_DISABLED |
359 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
360 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
361
362 ddr2->rtr = 0x2b0;
363
364 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
365 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
366 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
367 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
368 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
369 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
370 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
371 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
372
373 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
374 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
375 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
376 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
377
378 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
379 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
380 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
381 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
382 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
383}
384
385void mem_init(void)
386{
Wenyou Yangaa0a58d2016-02-01 18:12:15 +0800387 struct atmel_mpddrc_config ddr2;
Bo Shene47c0072014-12-15 13:24:39 +0800388
389 ddr2_conf(&ddr2);
390
Wenyou Yang78f89762016-02-03 10:16:50 +0800391 /* Enable MPDDR clock */
Bo Shene47c0072014-12-15 13:24:39 +0800392 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
Wenyou Yang78f89762016-02-03 10:16:50 +0800393 at91_system_clk_enable(AT91_PMC_DDR);
Bo Shene47c0072014-12-15 13:24:39 +0800394
395 /* DDRAM2 Controller initialize */
Erik van Luijk59d780a2015-08-13 15:43:18 +0200396 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
Bo Shene47c0072014-12-15 13:24:39 +0800397}
398
399void at91_pmc_init(void)
400{
Bo Shene47c0072014-12-15 13:24:39 +0800401 u32 tmp;
402
403 tmp = AT91_PMC_PLLAR_29 |
404 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
405 AT91_PMC_PLLXR_MUL(87) |
406 AT91_PMC_PLLXR_DIV(1);
407 at91_plla_init(tmp);
408
Wenyou Yang5265b1e2016-02-02 12:46:14 +0800409 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
Bo Shene47c0072014-12-15 13:24:39 +0800410
411 tmp = AT91_PMC_MCKR_H32MXDIV |
412 AT91_PMC_MCKR_PLLADIV_2 |
413 AT91_PMC_MCKR_MDIV_3 |
414 AT91_PMC_MCKR_CSS_PLLA;
415 at91_mck_init(tmp);
416}
417#endif