| Masahiro Yamada | c743249 | 2015-09-22 00:27:37 +0900 | [diff] [blame] | 1 | /* |
| 2 | * On-chip UART initializaion for low-level debugging |
| 3 | * |
| 4 | * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <linux/serial_reg.h> |
| 10 | #include <linux/linkage.h> |
| 11 | #include <mach/bcu-regs.h> |
| 12 | #include <mach/sc-regs.h> |
| 13 | #include <mach/sg-regs.h> |
| 14 | |
| 15 | #if !defined(CONFIG_DEBUG_SEMIHOSTING) |
| 16 | #include CONFIG_DEBUG_LL_INCLUDE |
| 17 | #endif |
| 18 | |
| 19 | #define BAUDRATE 115200 |
| 20 | #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) |
| 21 | |
| 22 | ENTRY(debug_ll_init) |
| 23 | ldr r0, =SG_REVISION |
| 24 | ldr r1, [r0] |
| 25 | and r1, r1, #SG_REVISION_TYPE_MASK |
| 26 | mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT |
| 27 | |
| 28 | #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) |
| 29 | #define PH1_SLD3_UART_CLK 36864000 |
| 30 | cmp r1, #0x25 |
| 31 | bne ph1_sld3_end |
| 32 | |
| 33 | sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0 |
| 34 | |
| 35 | ldr r0, =BCSCR5 |
| 36 | ldr r1, =0x24440000 |
| 37 | str r1, [r0] |
| 38 | |
| 39 | ldr r0, =SC_CLKCTRL |
| 40 | ldr r1, [r0] |
| 41 | orr r1, r1, #SC_CLKCTRL_CEN_PERI |
| 42 | str r1, [r0] |
| 43 | |
| 44 | ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE) |
| 45 | |
| 46 | b init_uart |
| 47 | ph1_sld3_end: |
| 48 | #endif |
| 49 | #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) |
| 50 | #define PH1_LD4_UART_CLK 36864000 |
| 51 | cmp r1, #0x26 |
| 52 | bne ph1_ld4_end |
| 53 | |
| 54 | ldr r0, =SG_IECTRL |
| 55 | ldr r1, [r0] |
| 56 | orr r1, r1, #1 |
| 57 | str r1, [r0] |
| 58 | |
| 59 | sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0 |
| 60 | |
| 61 | ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE) |
| 62 | |
| 63 | b init_uart |
| 64 | ph1_ld4_end: |
| 65 | #endif |
| 66 | #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) |
| 67 | #define PH1_PRO4_UART_CLK 73728000 |
| 68 | cmp r1, #0x28 |
| 69 | bne ph1_pro4_end |
| 70 | |
| 71 | sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 |
| 72 | |
| 73 | ldr r0, =SG_LOADPINCTRL |
| 74 | mov r1, #1 |
| 75 | str r1, [r0] |
| 76 | |
| 77 | ldr r0, =SC_CLKCTRL |
| 78 | ldr r1, [r0] |
| 79 | orr r1, r1, #SC_CLKCTRL_CEN_PERI |
| 80 | str r1, [r0] |
| 81 | |
| 82 | ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE) |
| 83 | |
| 84 | b init_uart |
| 85 | ph1_pro4_end: |
| 86 | #endif |
| 87 | #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) |
| 88 | #define PH1_SLD8_UART_CLK 80000000 |
| 89 | cmp r1, #0x29 |
| 90 | bne ph1_sld8_end |
| 91 | |
| 92 | ldr r0, =SG_IECTRL |
| 93 | ldr r1, [r0] |
| 94 | orr r1, r1, #1 |
| 95 | str r1, [r0] |
| 96 | |
| 97 | sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0 |
| 98 | |
| 99 | ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE) |
| 100 | |
| 101 | b init_uart |
| 102 | ph1_sld8_end: |
| 103 | #endif |
| 104 | |
| 105 | init_uart: |
| 106 | addruart r0, r1, r2 |
| 107 | mov r1, #UART_LCR_WLEN8 << 8 |
| 108 | str r1, [r0, #0x10] |
| 109 | str r3, [r0, #0x24] |
| 110 | |
| 111 | mov pc, lr |
| 112 | ENDPROC(debug_ll_init) |