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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha33913c52014-11-18 10:42:22 -08002/*
Patrice Chotardcc551162017-10-23 09:53:59 +02003 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha33913c52014-11-18 10:42:22 -08005 */
6
7#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glass495a5dc2019-11-14 12:57:30 -07009#include <time.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Vikas Manocha33913c52014-11-18 10:42:22 -080011#include <asm/io.h>
12#include <asm/arch-stv0991/hardware.h>
13#include <asm/arch-stv0991/stv0991_cgu.h>
14#include <asm/arch-stv0991/stv0991_gpt.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
Vikas Manocha33913c52014-11-18 10:42:22 -080016
17static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
18 (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
19
20#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
Patrick Delaunaya130b9c2021-10-06 18:10:32 +020021#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
Vikas Manocha33913c52014-11-18 10:42:22 -080022
23DECLARE_GLOBAL_DATA_PTR;
24
25#define timestamp gd->arch.tbl
26#define lastdec gd->arch.lastinc
27
Patrick Delaunay9858a602018-10-05 11:33:52 +020028static ulong get_timer_masked(void);
29
Vikas Manocha33913c52014-11-18 10:42:22 -080030int timer_init(void)
31{
32 /* Timer1 clock configuration */
33 writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
34 writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
35 TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
36
37 /* Stop the timer */
38 writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
39 writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
40 /* Configure timer for auto-reload */
41 writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
42 &gpt1_regs_ptr->cr1);
43
44 /* load value for free running */
45 writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
46
47 /* start timer */
48 writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
49 &gpt1_regs_ptr->cr1);
50
51 /* Reset the timer */
52 lastdec = READ_TIMER();
53 timestamp = 0;
54
55 return 0;
56}
57
58/*
59 * timer without interrupts
60 */
61ulong get_timer(ulong base)
62{
63 return (get_timer_masked() / GPT_RESOLUTION) - base;
64}
65
66void __udelay(unsigned long usec)
67{
68 ulong tmo;
69 ulong start = get_timer_masked();
Patrick Delaunaya130b9c2021-10-06 18:10:32 +020070 ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
Vikas Manocha33913c52014-11-18 10:42:22 -080071 ulong rndoff;
72
73 rndoff = (usec % 10) ? 1 : 0;
74
75 /* tenudelcnt timer tick gives 10 microsecconds delay */
76 tmo = ((usec / 10) + rndoff) * tenudelcnt;
77
78 while ((ulong) (get_timer_masked() - start) < tmo)
79 ;
80}
81
Patrick Delaunay9858a602018-10-05 11:33:52 +020082static ulong get_timer_masked(void)
Vikas Manocha33913c52014-11-18 10:42:22 -080083{
84 ulong now = READ_TIMER();
85
86 if (now >= lastdec) {
87 /* normal mode */
88 timestamp += now - lastdec;
89 } else {
90 /* we have an overflow ... */
91 timestamp += now + GPT_FREE_RUNNING - lastdec;
92 }
93 lastdec = now;
94
95 return timestamp;
96}
97
Vikas Manocha33913c52014-11-18 10:42:22 -080098/*
99 * This function is derived from PowerPC code (read timebase as long long).
100 * On ARM it just returns the timer value.
101 */
102unsigned long long get_ticks(void)
103{
104 return get_timer(0);
105}
106
107/*
108 * This function is derived from PowerPC code (timebase clock frequency).
109 * On ARM it returns the number of timer ticks per second.
110 */
111ulong get_tbclk(void)
112{
Patrick Delaunaya130b9c2021-10-06 18:10:32 +0200113 return CONFIG_SYS_HZ;
Vikas Manocha33913c52014-11-18 10:42:22 -0800114}