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git01.mediatek.com / filogic / uboot / d47dffedf6acd3373ef913838d5d817db7eba269 / . / arch / arm / cpu / pxa / usb.c
blob: c31c2d73390eef5fefa6d135c649fce04db888d7 [file] [log] [blame]
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]1/*
2 * (C) Copyright 2006
3 * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]6 */
7
8#include <common.h>
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]9
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]10#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]11# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
Markus Klotzbuecherd0a38782006-05-23 13:38:35 +0200[diff] [blame]12
13#include <asm/arch/pxa-regs.h>
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]14#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARDbce7b142007-10-19 10:55:24 +0200[diff] [blame]15#include <usb.h>
Markus Klotzbuecherd0a38782006-05-23 13:38:35 +0200[diff] [blame]16
Jean-Christophe PLAGNIOL-VILLARD733fc372007-10-19 08:10:15 +0200[diff] [blame]17int usb_cpu_init(void)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]18{
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]19#if defined(CONFIG_CPU_MONAHANS)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]20 /* Enable USB host clock. */
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]21 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]22 udelay(100);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]23#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]24#if defined(CONFIG_CPU_PXA27X)
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]25 /* Enable USB host clock. */
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]26 writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]27#endif
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]28
Markus Klotzbuecher4a7847b2007-04-03 14:27:08 +0200[diff] [blame]29#if defined(CONFIG_CPU_MONAHANS)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]30 /* Configure Port 2 for Host (USB Client Registers) */
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]31 writel(0x3000c, UP2OCR);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]32#endif
33
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]34 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
Mike Frysinger60ce19a2012-03-05 13:47:00 +0000[diff] [blame]35 mdelay(11);
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]36 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]37
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]38 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
39 while (readl(UHCHR) & UHCHR_FSBIR)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]40 udelay(1);
41
Stefan Herbrechtsmeier13d240f2011-10-17 17:22:47 +0200[diff] [blame]42#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]43 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]44#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]45#if defined(CONFIG_CPU_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]46 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]47#endif
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]48 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]49
50 return 0;
51}
52
Jean-Christophe PLAGNIOL-VILLARD733fc372007-10-19 08:10:15 +0200[diff] [blame]53int usb_cpu_stop(void)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]54{
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]55 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]56 udelay(11);
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]57 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]58
Stefan Herbrechtsmeier38f79c62011-10-17 17:22:46 +0200[diff] [blame]59 writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]60 udelay(10);
61
Stefan Herbrechtsmeier13d240f2011-10-17 17:22:47 +0200[diff] [blame]62#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]63 writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]64#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]65#if defined(CONFIG_CPU_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]66 writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]67#endif
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]68 writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]69
70#if defined(CONFIG_CPU_MONAHANS)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]71 /* Disable USB host clock. */
72 writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
73 udelay(100);
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]74#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]75#if defined(CONFIG_CPU_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]76 /* Disable USB host clock. */
77 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]78#endif
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]79
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]80 return 0;
81}
Markus Klotzbuecheraa219212006-05-30 16:56:14 +0200[diff] [blame]82
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]83int usb_cpu_init_fail(void)
84{
85 return usb_cpu_stop();
86}
87
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]88# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]89#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */