blob: 8081d0cd82f3d0aa33b0365b9e6d1988308e6dff [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0
York Sunf0626592013-09-30 09:22:09 -07002#
York Sun2896cb72014-03-27 17:54:47 -07003# Copyright 2008-2014 Freescale Semiconductor, Inc.
York Sunf0626592013-09-30 09:22:09 -07004
York Sun2896cb72014-03-27 17:54:47 -07005obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
6 lc_common_dimm_params.o
7obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
8 lc_common_dimm_params.o
9obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
10 lc_common_dimm_params.o
11obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \
12 lc_common_dimm_params.o
York Sunf0626592013-09-30 09:22:09 -070013
York Sunf0626592013-09-30 09:22:09 -070014ifdef CONFIG_DDR_SPD
15SPD := y
16endif
17ifdef CONFIG_SPD_EEPROM
18SPD := y
19endif
20ifdef SPD
21obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
22obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
23obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
York Sun2896cb72014-03-27 17:54:47 -070024obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o
York Sunf0626592013-09-30 09:22:09 -070025endif
26
27obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
28obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
29obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
30obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
York Sun461c9392013-09-30 14:20:51 -070031obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
York Sun2896cb72014-03-27 17:54:47 -070032obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
Shengzhou Liucb7fb122016-08-26 18:30:39 +080033obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o