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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Max Krummenachereeb16b22016-11-30 19:43:09 +01002/*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +01005 * Copyright (C) 2014-2019, Toradex AG
Max Krummenachereeb16b22016-11-30 19:43:09 +01006 * copied from nitrogen6x
Max Krummenachereeb16b22016-11-30 19:43:09 +01007 */
8
9#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glass11c89f32017-05-17 17:18:03 -060011#include <dm.h>
Simon Glass6eaea252019-08-01 09:46:48 -060012#include <env.h>
Simon Glassa7b51302019-11-14 12:57:46 -070013#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060014#include <net.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +010018
Max Krummenachereeb16b22016-11-30 19:43:09 +010019#include <asm/arch/clock.h>
20#include <asm/arch/crm_regs.h>
21#include <asm/arch/imx-regs.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010022#include <asm/arch/mx6-ddr.h>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +010023#include <asm/arch/mx6-pins.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010024#include <asm/arch/mxc_hdmi.h>
25#include <asm/arch/sys_proto.h>
26#include <asm/bootm.h>
27#include <asm/gpio.h>
Marcel Ziswiler3e43a502019-02-08 18:42:10 +010028#include <asm/mach-imx/boot_mode.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020029#include <asm/mach-imx/iomux-v3.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020030#include <asm/mach-imx/sata.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020031#include <asm/mach-imx/video.h>
Shiji Yangbb112342023-08-03 09:47:16 +080032#include <asm/sections.h>
Bhuvanchandra DVcd6072c2019-02-08 18:42:24 +010033#include <cpu.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010034#include <dm/platform_data/serial_mxc.h>
Yangbo Lu73340382019-06-21 11:42:28 +080035#include <fsl_esdhc_imx.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010036#include <imx_thermal.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010037#include <miiphy.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010038#include <netdev.h>
Gerard Salvatella7fba5092019-02-08 18:42:28 +010039#include <cpu.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +010040
41#include "../common/tdx-cfg-block.h"
42#ifdef CONFIG_TDX_CMD_IMX_MFGR
43#include "pf0100.h"
44#endif
45
46DECLARE_GLOBAL_DATA_PTR;
47
48#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
Max Krummenachera0f4d792019-02-08 18:42:19 +010053 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55
56#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
Max Krummenachereeb16b22016-11-30 19:43:09 +010057 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
58 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
59
Max Krummenachereeb16b22016-11-30 19:43:09 +010060#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
62 PAD_CTL_SRE_SLOW)
63
64#define NO_PULLUP ( \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
66 PAD_CTL_SRE_SLOW)
67
68#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
69 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
70 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
71
Max Krummenachereeb16b22016-11-30 19:43:09 +010072#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
73
74int dram_init(void)
75{
76 /* use the DDR controllers configured size */
Tom Rinibb4dd962022-11-16 13:10:37 -050077 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
Max Krummenachereeb16b22016-11-30 19:43:09 +010078 (ulong)imx_ddr_size());
79
80 return 0;
81}
82
83/* Colibri UARTA */
84iomux_v3_cfg_t const uart1_pads[] = {
85 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87};
88
Igor Opaniuk6c6a9862019-12-06 18:24:16 +020089#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
Marcel Ziswilerc882cfb2019-02-08 18:42:12 +010090/* Colibri MMC */
Max Krummenachereeb16b22016-11-30 19:43:09 +010091iomux_v3_cfg_t const usdhc1_pads[] = {
92 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
99# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
100};
101
102/* eMMC */
103iomux_v3_cfg_t const usdhc3_pads[] = {
Max Krummenachera0f4d792019-02-08 18:42:19 +0100104 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
105 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
106 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
107 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
108 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
109 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
110 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
111 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
112 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
113 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
Max Krummenachereeb16b22016-11-30 19:43:09 +0100114 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115};
Yangbo Lu73340382019-06-21 11:42:28 +0800116#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100117
Max Krummenachereeb16b22016-11-30 19:43:09 +0100118/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
119iomux_v3_cfg_t const gpio_pads[] = {
120 /* ADDRESS[17:18] [25] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100121 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
122 MUX_MODE_SION,
123 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
124 MUX_MODE_SION,
125 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
126 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100127 /* ADDRESS[19:24] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100128 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
129 MUX_MODE_SION,
130 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
131 MUX_MODE_SION,
132 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
133 MUX_MODE_SION,
134 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
135 MUX_MODE_SION,
136 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
137 MUX_MODE_SION,
138 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
139 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100140 /* DATA[16:29] [31] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100141 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
142 MUX_MODE_SION,
143 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
144 MUX_MODE_SION,
145 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
146 MUX_MODE_SION,
147 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
148 MUX_MODE_SION,
149 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
150 MUX_MODE_SION,
151 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
152 MUX_MODE_SION,
153 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
154 MUX_MODE_SION,
155 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
156 MUX_MODE_SION,
157 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
158 MUX_MODE_SION,
159 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
160 MUX_MODE_SION,
161 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
162 MUX_MODE_SION,
163 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
164 MUX_MODE_SION,
165 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
166 MUX_MODE_SION,
167 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
168 MUX_MODE_SION,
169 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
170 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100171 /* DQM[0:3] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100172 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
173 MUX_MODE_SION,
174 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
175 MUX_MODE_SION,
176 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
177 MUX_MODE_SION,
178 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
179 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100180 /* RDY used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100181 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
182 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100183 /* ADDRESS[16] DATA[30] used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100184 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
185 MUX_MODE_SION,
186 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
187 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100188 /* CSI pins used as GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100189 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
190 MUX_MODE_SION,
191 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
192 MUX_MODE_SION,
193 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
194 MUX_MODE_SION,
195 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
196 MUX_MODE_SION,
197 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
198 MUX_MODE_SION,
199 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
200 MUX_MODE_SION,
201 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
202 MUX_MODE_SION,
203 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
204 MUX_MODE_SION,
205 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
206 MUX_MODE_SION,
207 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
208 MUX_MODE_SION,
209 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
210 MUX_MODE_SION,
211 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
212 MUX_MODE_SION,
213 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
214 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100215 /* GPIO */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100216 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
217 MUX_MODE_SION,
218 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
219 MUX_MODE_SION,
220 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
221 MUX_MODE_SION,
222 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
223 MUX_MODE_SION,
224 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
225 MUX_MODE_SION,
226 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
227 MUX_MODE_SION,
228 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
229 MUX_MODE_SION,
230 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
231 MUX_MODE_SION,
232 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
233 MUX_MODE_SION,
234 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
235 MUX_MODE_SION,
236 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
237 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100238 /* USBH_OC */
239 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
240 /* USBC_ID */
241 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
242 /* USBC_DET */
243 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
244};
245
246static void setup_iomux_gpio(void)
247{
248 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
249}
250
251iomux_v3_cfg_t const usb_pads[] = {
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100252 /* USBH_PEN */
253 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100254# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
255};
256
257/*
258 * UARTs are used in DTE mode, switch the mode on all UARTs before
259 * any pinmuxing connects a (DCE) output to a transceiver output.
260 */
Max Krummenacher003bc132019-02-08 18:42:21 +0100261#define UCR3 0x88 /* FIFO Control Register */
262#define UCR3_RI BIT(8) /* RIDELT DTE mode */
263#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100264#define UFCR 0x90 /* FIFO Control Register */
Max Krummenacher003bc132019-02-08 18:42:21 +0100265#define UFCR_DCEDTE BIT(6) /* DCE=0 */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100266
267static void setup_dtemode_uart(void)
268{
269 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
270 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
271 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
Max Krummenacher003bc132019-02-08 18:42:21 +0100272
273 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
274 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
275 clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100276}
277
278static void setup_iomux_uart(void)
279{
280 setup_dtemode_uart();
281 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
282}
283
284#ifdef CONFIG_USB_EHCI_MX6
285int board_ehci_hcd_init(int port)
286{
287 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
288 return 0;
289}
Marcel Ziswilerf2839442019-02-08 18:42:15 +0100290#endif
Max Krummenachereeb16b22016-11-30 19:43:09 +0100291
Igor Opaniuk6c6a9862019-12-06 18:24:16 +0200292#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100293/* use the following sequence: eMMC, MMC */
Tom Rini376b88a2022-10-28 20:27:13 -0400294struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
Max Krummenachereeb16b22016-11-30 19:43:09 +0100295 {USDHC3_BASE_ADDR},
296 {USDHC1_BASE_ADDR},
297};
298
299int board_mmc_getcd(struct mmc *mmc)
300{
301 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
302 int ret = true; /* default: assume inserted */
303
304 switch (cfg->esdhc_base) {
305 case USDHC1_BASE_ADDR:
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100306 gpio_request(GPIO_MMC_CD, "MMC_CD");
Max Krummenachereeb16b22016-11-30 19:43:09 +0100307 gpio_direction_input(GPIO_MMC_CD);
308 ret = !gpio_get_value(GPIO_MMC_CD);
309 break;
310 }
311
312 return ret;
313}
314
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900315int board_mmc_init(struct bd_info *bis)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100316{
Max Krummenachereeb16b22016-11-30 19:43:09 +0100317 struct src *psrc = (struct src *)SRC_BASE_ADDR;
318 unsigned reg = readl(&psrc->sbmr1) >> 11;
319 /*
320 * Upon reading BOOT_CFG register the following map is done:
321 * Bit 11 and 12 of BOOT_CFG register can determine the current
322 * mmc port
323 * 0x1 SD1
324 * 0x2 SD2
325 * 0x3 SD4
326 */
327
328 switch (reg & 0x3) {
329 case 0x0:
330 imx_iomux_v3_setup_multiple_pads(
331 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
332 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
333 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
334 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
335 break;
336 case 0x2:
337 imx_iomux_v3_setup_multiple_pads(
338 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
339 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
340 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
341 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
342 break;
343 default:
344 puts("MMC boot device not available");
345 }
346
347 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100348}
Yangbo Lu73340382019-06-21 11:42:28 +0800349#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
Max Krummenachereeb16b22016-11-30 19:43:09 +0100350
351int board_phy_config(struct phy_device *phydev)
352{
353 if (phydev->drv->config)
354 phydev->drv->config(phydev);
355
356 return 0;
357}
358
Igor Opaniuk03e68cd2019-11-04 11:12:00 +0100359int setup_fec(void)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100360{
Max Krummenachereeb16b22016-11-30 19:43:09 +0100361 int ret;
Igor Opaniuka022ba32020-03-27 12:28:17 +0200362 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
Max Krummenachereeb16b22016-11-30 19:43:09 +0100363
364 /* provide the PHY clock from the i.MX 6 */
365 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
366 if (ret)
367 return ret;
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100368
Igor Opaniuka022ba32020-03-27 12:28:17 +0200369 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
370
Max Krummenachereeb16b22016-11-30 19:43:09 +0100371 return 0;
372}
373
374static iomux_v3_cfg_t const pwr_intb_pads[] = {
375 /*
376 * the bootrom sets the iomux to vselect, potentially connecting
377 * two outputs. Set this back to GPIO
378 */
379 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
380};
381
382#if defined(CONFIG_VIDEO_IPUV3)
383
384static iomux_v3_cfg_t const backlight_pads[] = {
385 /* Backlight On */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100386 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100387#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
388 /* Backlight PWM, used as GPIO in U-Boot */
389 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100390 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
391 MUX_MODE_SION,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100392#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
393};
394
395static iomux_v3_cfg_t const rgb_pads[] = {
396 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
397 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
398 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
399 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
400 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
401 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
402 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
403 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
404 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
405 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
406 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
407 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
408 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
409 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
410 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
411 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
412 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
413 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
414 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
415 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
416 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
417 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
418};
419
420static void do_enable_hdmi(struct display_info_t const *dev)
421{
422 imx_enable_hdmi_phy();
423}
424
425static void enable_rgb(struct display_info_t const *dev)
426{
427 imx_iomux_v3_setup_multiple_pads(
428 rgb_pads,
429 ARRAY_SIZE(rgb_pads));
430 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
431 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
432}
433
434static int detect_default(struct display_info_t const *dev)
435{
436 (void) dev;
437 return 1;
438}
439
440struct display_info_t const displays[] = {{
441 .bus = -1,
442 .addr = 0,
443 .pixfmt = IPU_PIX_FMT_RGB24,
444 .detect = detect_hdmi,
445 .enable = do_enable_hdmi,
446 .mode = {
447 .name = "HDMI",
448 .refresh = 60,
449 .xres = 1024,
450 .yres = 768,
451 .pixclock = 15385,
452 .left_margin = 220,
453 .right_margin = 40,
454 .upper_margin = 21,
455 .lower_margin = 7,
456 .hsync_len = 60,
457 .vsync_len = 10,
458 .sync = FB_SYNC_EXT,
459 .vmode = FB_VMODE_NONINTERLACED
460} }, {
461 .bus = -1,
462 .addr = 0,
463 .pixfmt = IPU_PIX_FMT_RGB666,
464 .detect = detect_default,
465 .enable = enable_rgb,
466 .mode = {
467 .name = "vga-rgb",
468 .refresh = 60,
469 .xres = 640,
470 .yres = 480,
471 .pixclock = 33000,
472 .left_margin = 48,
473 .right_margin = 16,
474 .upper_margin = 31,
475 .lower_margin = 11,
476 .hsync_len = 96,
477 .vsync_len = 2,
478 .sync = 0,
479 .vmode = FB_VMODE_NONINTERLACED
480} }, {
481 .bus = -1,
482 .addr = 0,
483 .pixfmt = IPU_PIX_FMT_RGB666,
484 .enable = enable_rgb,
485 .mode = {
486 .name = "wvga-rgb",
487 .refresh = 60,
488 .xres = 800,
489 .yres = 480,
490 .pixclock = 25000,
491 .left_margin = 40,
492 .right_margin = 88,
493 .upper_margin = 33,
494 .lower_margin = 10,
495 .hsync_len = 128,
496 .vsync_len = 2,
497 .sync = 0,
498 .vmode = FB_VMODE_NONINTERLACED
499} } };
500size_t display_count = ARRAY_SIZE(displays);
501
502static void setup_display(void)
503{
504 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
505 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
506 int reg;
507
508 enable_ipu_clock();
509 imx_setup_hdmi();
510 /* Turn on LDB0,IPU,IPU DI0 clocks */
511 reg = __raw_readl(&mxc_ccm->CCGR3);
512 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
513 writel(reg, &mxc_ccm->CCGR3);
514
515 /* set LDB0, LDB1 clk select to 011/011 */
516 reg = readl(&mxc_ccm->cs2cdr);
517 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
518 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
519 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
520 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
521 writel(reg, &mxc_ccm->cs2cdr);
522
523 reg = readl(&mxc_ccm->cscmr2);
524 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
525 writel(reg, &mxc_ccm->cscmr2);
526
527 reg = readl(&mxc_ccm->chsccdr);
528 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
529 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
530 writel(reg, &mxc_ccm->chsccdr);
531
532 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
533 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
534 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
535 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
536 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
537 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
538 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
539 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
540 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
541 writel(reg, &iomux->gpr[2]);
542
543 reg = readl(&iomux->gpr[3]);
544 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
545 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
546 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
547 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
548 writel(reg, &iomux->gpr[3]);
549
550 /* backlight unconditionally on for now */
551 imx_iomux_v3_setup_multiple_pads(backlight_pads,
552 ARRAY_SIZE(backlight_pads));
553 /* use 0 for EDT 7", use 1 for LG fullHD panel */
Marcel Ziswiler3e43a502019-02-08 18:42:10 +0100554 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
555 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
Max Krummenachereeb16b22016-11-30 19:43:09 +0100556 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
557 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
558}
Gerard Salvatella108d7392018-11-19 15:54:10 +0100559
560/*
561 * Backlight off before OS handover
562 */
563void board_preboot_os(void)
564{
565 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
566 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
567}
Max Krummenachereeb16b22016-11-30 19:43:09 +0100568#endif /* defined(CONFIG_VIDEO_IPUV3) */
569
570int board_early_init_f(void)
571{
572 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
573 ARRAY_SIZE(pwr_intb_pads));
574 setup_iomux_uart();
575
Max Krummenachereeb16b22016-11-30 19:43:09 +0100576 return 0;
577}
578
579/*
580 * Do not overwrite the console
581 * Use always serial for U-Boot console
582 */
583int overwrite_console(void)
584{
585 return 1;
586}
587
588int board_init(void)
589{
590 /* address of boot parameters */
591 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
Igor Opaniuk03e68cd2019-11-04 11:12:00 +0100592#if defined(CONFIG_FEC_MXC)
593 setup_fec();
594#endif
Fabio Estevamfd2525a2017-09-22 23:45:33 -0300595#if defined(CONFIG_VIDEO_IPUV3)
596 setup_display();
597#endif
598
Max Krummenachereeb16b22016-11-30 19:43:09 +0100599#ifdef CONFIG_TDX_CMD_IMX_MFGR
600 (void) pmic_init();
601#endif
602
Simon Glassab3055a2017-06-14 21:28:25 -0600603#ifdef CONFIG_SATA
Max Krummenachereeb16b22016-11-30 19:43:09 +0100604 setup_sata();
605#endif
606
607 setup_iomux_gpio();
608
609 return 0;
610}
611
612#ifdef CONFIG_BOARD_LATE_INIT
613int board_late_init(void)
614{
Tom Rini4cc38852021-08-30 09:16:30 -0400615#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100616 char env_str[256];
617 u32 rev;
618
Tom Rini4cc38852021-08-30 09:16:30 -0400619 rev = get_board_revision();
Max Krummenachereeb16b22016-11-30 19:43:09 +0100620 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
Simon Glass6a38e412017-08-03 12:22:09 -0600621 env_set("board_rev", env_str);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100622#endif
623
Stefan Agnerea8e2e92019-02-08 18:42:26 +0100624#ifdef CONFIG_CMD_USB_SDP
625 if (is_boot_from_usb()) {
626 printf("Serial Downloader recovery mode, using sdp command\n");
627 env_set("bootdelay", "0");
628 env_set("bootcmd", "sdp 0");
629 }
630#endif /* CONFIG_CMD_USB_SDP */
631
Max Krummenachereeb16b22016-11-30 19:43:09 +0100632 return 0;
633}
634#endif /* CONFIG_BOARD_LATE_INIT */
635
Max Krummenachereeb16b22016-11-30 19:43:09 +0100636int checkboard(void)
637{
638 char it[] = " IT";
639 int minc, maxc;
640
641 switch (get_cpu_temp_grade(&minc, &maxc)) {
642 case TEMP_AUTOMOTIVE:
643 case TEMP_INDUSTRIAL:
644 break;
645 case TEMP_EXTCOMMERCIAL:
646 default:
647 it[0] = 0;
648 };
649 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
650 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
651 (gd->ram_size == 0x20000000) ? "512" : "256", it);
652 return 0;
653}
654
655#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900656int ft_board_setup(void *blob, struct bd_info *bd)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100657{
Bhuvanchandra DVcd6072c2019-02-08 18:42:24 +0100658 u32 cma_size;
659
660 ft_common_board_setup(blob, bd);
661
Stefan Agnerea8e2e92019-02-08 18:42:26 +0100662 cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
Bhuvanchandra DVcd6072c2019-02-08 18:42:24 +0100663 cma_size = min((u32)(gd->ram_size >> 1), cma_size);
664
665 fdt_setprop_u32(blob,
666 fdt_path_offset(blob, "/reserved-memory/linux,cma"),
667 "size",
668 cma_size);
669 return 0;
Max Krummenachereeb16b22016-11-30 19:43:09 +0100670}
671#endif
672
673#ifdef CONFIG_CMD_BMODE
674static const struct boot_mode board_boot_modes[] = {
675 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
676 {NULL, 0},
677};
678#endif
679
680int misc_init_r(void)
681{
682#ifdef CONFIG_CMD_BMODE
683 add_board_boot_modes(board_boot_modes);
684#endif
685 return 0;
686}
687
688#ifdef CONFIG_LDO_BYPASS_CHECK
689/* TODO, use external pmic, for now always ldo_enable */
690void ldo_mode_set(int ldo_bypass)
691{
692 return;
693}
694#endif
695
696#ifdef CONFIG_SPL_BUILD
697#include <spl.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +0900698#include <linux/libfdt.h>
Max Krummenachereeb16b22016-11-30 19:43:09 +0100699#include "asm/arch/mx6dl-ddr.h"
700#include "asm/arch/iomux.h"
701#include "asm/arch/crm_regs.h"
702
703static int mx6s_dcd_table[] = {
704/* ddr-setup.cfg */
705
706MX6_IOM_DRAM_SDQS0, 0x00000030,
707MX6_IOM_DRAM_SDQS1, 0x00000030,
708MX6_IOM_DRAM_SDQS2, 0x00000030,
709MX6_IOM_DRAM_SDQS3, 0x00000030,
710MX6_IOM_DRAM_SDQS4, 0x00000030,
711MX6_IOM_DRAM_SDQS5, 0x00000030,
712MX6_IOM_DRAM_SDQS6, 0x00000030,
713MX6_IOM_DRAM_SDQS7, 0x00000030,
714
715MX6_IOM_GRP_B0DS, 0x00000030,
716MX6_IOM_GRP_B1DS, 0x00000030,
717MX6_IOM_GRP_B2DS, 0x00000030,
718MX6_IOM_GRP_B3DS, 0x00000030,
719MX6_IOM_GRP_B4DS, 0x00000030,
720MX6_IOM_GRP_B5DS, 0x00000030,
721MX6_IOM_GRP_B6DS, 0x00000030,
722MX6_IOM_GRP_B7DS, 0x00000030,
723MX6_IOM_GRP_ADDDS, 0x00000030,
724/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
725MX6_IOM_GRP_CTLDS, 0x00000030,
726
727MX6_IOM_DRAM_DQM0, 0x00020030,
728MX6_IOM_DRAM_DQM1, 0x00020030,
729MX6_IOM_DRAM_DQM2, 0x00020030,
730MX6_IOM_DRAM_DQM3, 0x00020030,
731MX6_IOM_DRAM_DQM4, 0x00020030,
732MX6_IOM_DRAM_DQM5, 0x00020030,
733MX6_IOM_DRAM_DQM6, 0x00020030,
734MX6_IOM_DRAM_DQM7, 0x00020030,
735
736MX6_IOM_DRAM_CAS, 0x00020030,
737MX6_IOM_DRAM_RAS, 0x00020030,
738MX6_IOM_DRAM_SDCLK_0, 0x00020030,
739MX6_IOM_DRAM_SDCLK_1, 0x00020030,
740
741MX6_IOM_DRAM_RESET, 0x00020030,
742MX6_IOM_DRAM_SDCKE0, 0x00003000,
743MX6_IOM_DRAM_SDCKE1, 0x00003000,
744
745MX6_IOM_DRAM_SDODT0, 0x00003030,
746MX6_IOM_DRAM_SDODT1, 0x00003030,
747
748/* (differential input) */
749MX6_IOM_DDRMODE_CTL, 0x00020000,
750/* (differential input) */
751MX6_IOM_GRP_DDRMODE, 0x00020000,
752/* disable ddr pullups */
753MX6_IOM_GRP_DDRPKE, 0x00000000,
754MX6_IOM_DRAM_SDBA2, 0x00000000,
755/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
756MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
757
758/* Read data DQ Byte0-3 delay */
759MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
760MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
761MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
762MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
763MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
764MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
765MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
766MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
767
768/*
769 * MDMISC mirroring interleaved (row/bank/col)
770 */
Stefan Eichenbergera817bcb2023-06-14 11:01:37 +0200771MX6_MMDC_P0_MDMISC, 0x000b17c0,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100772
773/*
774 * MDSCR con_req
775 */
776MX6_MMDC_P0_MDSCR, 0x00008000,
777
778
779/* 800mhz_2x64mx16.cfg */
780
781MX6_MMDC_P0_MDPDC, 0x0002002D,
782MX6_MMDC_P0_MDCFG0, 0x2C305503,
783MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
784MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
785MX6_MMDC_P0_MDRWD, 0x000026D2,
786MX6_MMDC_P0_MDOR, 0x00301023,
787MX6_MMDC_P0_MDOTC, 0x00333030,
788MX6_MMDC_P0_MDPDC, 0x0002556D,
789/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
790MX6_MMDC_P0_MDASP, 0x00000017,
791/* DDR3 DATA BUS SIZE: 64BIT */
792/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
793/* DDR3 DATA BUS SIZE: 32BIT */
794MX6_MMDC_P0_MDCTL, 0x82190000,
795
796/* Write commands to DDR */
797/* Load Mode Registers */
798/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
799/* MX6_MMDC_P0_MDSCR, 0x04408032, */
800MX6_MMDC_P0_MDSCR, 0x04008032,
801MX6_MMDC_P0_MDSCR, 0x00008033,
802MX6_MMDC_P0_MDSCR, 0x00048031,
803MX6_MMDC_P0_MDSCR, 0x13208030,
804/* ZQ calibration */
805MX6_MMDC_P0_MDSCR, 0x04008040,
806
807MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
808MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
809MX6_MMDC_P0_MDREF, 0x00005800,
810
811MX6_MMDC_P0_MPODTCTRL, 0x00000000,
812MX6_MMDC_P1_MPODTCTRL, 0x00000000,
813
814MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
815MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
816MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
817MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
818
819MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
820MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
821MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
822MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
823
824MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
825MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
826MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
827MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
828
829MX6_MMDC_P0_MPMUR0, 0x00000800,
830MX6_MMDC_P1_MPMUR0, 0x00000800,
831MX6_MMDC_P0_MDSCR, 0x00000000,
832MX6_MMDC_P0_MAPSR, 0x00011006,
833};
834
835static int mx6dl_dcd_table[] = {
836/* ddr-setup.cfg */
837
838MX6_IOM_DRAM_SDQS0, 0x00000030,
839MX6_IOM_DRAM_SDQS1, 0x00000030,
840MX6_IOM_DRAM_SDQS2, 0x00000030,
841MX6_IOM_DRAM_SDQS3, 0x00000030,
842MX6_IOM_DRAM_SDQS4, 0x00000030,
843MX6_IOM_DRAM_SDQS5, 0x00000030,
844MX6_IOM_DRAM_SDQS6, 0x00000030,
845MX6_IOM_DRAM_SDQS7, 0x00000030,
846
847MX6_IOM_GRP_B0DS, 0x00000030,
848MX6_IOM_GRP_B1DS, 0x00000030,
849MX6_IOM_GRP_B2DS, 0x00000030,
850MX6_IOM_GRP_B3DS, 0x00000030,
851MX6_IOM_GRP_B4DS, 0x00000030,
852MX6_IOM_GRP_B5DS, 0x00000030,
853MX6_IOM_GRP_B6DS, 0x00000030,
854MX6_IOM_GRP_B7DS, 0x00000030,
855MX6_IOM_GRP_ADDDS, 0x00000030,
856/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
857MX6_IOM_GRP_CTLDS, 0x00000030,
858
859MX6_IOM_DRAM_DQM0, 0x00020030,
860MX6_IOM_DRAM_DQM1, 0x00020030,
861MX6_IOM_DRAM_DQM2, 0x00020030,
862MX6_IOM_DRAM_DQM3, 0x00020030,
863MX6_IOM_DRAM_DQM4, 0x00020030,
864MX6_IOM_DRAM_DQM5, 0x00020030,
865MX6_IOM_DRAM_DQM6, 0x00020030,
866MX6_IOM_DRAM_DQM7, 0x00020030,
867
868MX6_IOM_DRAM_CAS, 0x00020030,
869MX6_IOM_DRAM_RAS, 0x00020030,
870MX6_IOM_DRAM_SDCLK_0, 0x00020030,
871MX6_IOM_DRAM_SDCLK_1, 0x00020030,
872
873MX6_IOM_DRAM_RESET, 0x00020030,
874MX6_IOM_DRAM_SDCKE0, 0x00003000,
875MX6_IOM_DRAM_SDCKE1, 0x00003000,
876
877MX6_IOM_DRAM_SDODT0, 0x00003030,
878MX6_IOM_DRAM_SDODT1, 0x00003030,
879
880/* (differential input) */
881MX6_IOM_DDRMODE_CTL, 0x00020000,
882/* (differential input) */
883MX6_IOM_GRP_DDRMODE, 0x00020000,
884/* disable ddr pullups */
885MX6_IOM_GRP_DDRPKE, 0x00000000,
886MX6_IOM_DRAM_SDBA2, 0x00000000,
887/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
888MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
889
890/* Read data DQ Byte0-3 delay */
891MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
892MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
893MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
894MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
895MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
896MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
897MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
898MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
899
900/*
901 * MDMISC mirroring interleaved (row/bank/col)
902 */
Stefan Eichenbergera817bcb2023-06-14 11:01:37 +0200903MX6_MMDC_P0_MDMISC, 0x000b17c0,
Max Krummenachereeb16b22016-11-30 19:43:09 +0100904
905/*
906 * MDSCR con_req
907 */
908MX6_MMDC_P0_MDSCR, 0x00008000,
909
910
911/* 800mhz_2x64mx16.cfg */
912
913MX6_MMDC_P0_MDPDC, 0x0002002D,
914MX6_MMDC_P0_MDCFG0, 0x2C305503,
915MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
916MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
917MX6_MMDC_P0_MDRWD, 0x000026D2,
918MX6_MMDC_P0_MDOR, 0x00301023,
919MX6_MMDC_P0_MDOTC, 0x00333030,
920MX6_MMDC_P0_MDPDC, 0x0002556D,
921/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
922MX6_MMDC_P0_MDASP, 0x00000017,
923/* DDR3 DATA BUS SIZE: 64BIT */
924MX6_MMDC_P0_MDCTL, 0x821A0000,
925/* DDR3 DATA BUS SIZE: 32BIT */
926/* MX6_MMDC_P0_MDCTL, 0x82190000, */
927
928/* Write commands to DDR */
929/* Load Mode Registers */
930/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
931/* MX6_MMDC_P0_MDSCR, 0x04408032, */
932MX6_MMDC_P0_MDSCR, 0x04008032,
933MX6_MMDC_P0_MDSCR, 0x00008033,
934MX6_MMDC_P0_MDSCR, 0x00048031,
935MX6_MMDC_P0_MDSCR, 0x13208030,
936/* ZQ calibration */
937MX6_MMDC_P0_MDSCR, 0x04008040,
938
939MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
940MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
941MX6_MMDC_P0_MDREF, 0x00005800,
942
943MX6_MMDC_P0_MPODTCTRL, 0x00000000,
944MX6_MMDC_P1_MPODTCTRL, 0x00000000,
945
946MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
947MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
948MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
949MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
950
951MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
952MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
953MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
954MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
955
956MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
957MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
958MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
959MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
960
961MX6_MMDC_P0_MPMUR0, 0x00000800,
962MX6_MMDC_P1_MPMUR0, 0x00000800,
963MX6_MMDC_P0_MDSCR, 0x00000000,
964MX6_MMDC_P0_MAPSR, 0x00011006,
965};
966
967static void ccgr_init(void)
968{
969 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
970
971 writel(0x00C03F3F, &ccm->CCGR0);
972 writel(0x0030FC03, &ccm->CCGR1);
973 writel(0x0FFFFFF3, &ccm->CCGR2);
974 writel(0x3FF0300F, &ccm->CCGR3);
975 writel(0x00FFF300, &ccm->CCGR4);
976 writel(0x0F0000F3, &ccm->CCGR5);
977 writel(0x000003FF, &ccm->CCGR6);
978
979/*
980 * Setup CCM_CCOSR register as follows:
981 *
Francesco Dolcini1fb07132022-06-24 11:52:19 +0200982 * clko2_en = 1 --> CKO2 enabled
983 * clko2_div = 000 --> divide by 1
984 * clko2_sel = 01110 --> osc_clk (24MHz)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100985 *
Francesco Dolcini1fb07132022-06-24 11:52:19 +0200986 * clk_out_sel = 1 --> Output CKO2 to CKO1
987 *
988 * This sets both CLKO2/CLKO1 output to 24MHz,
989 * CLKO1 configuration not relevant because of clk_out_sel
990 * (CLKO1 set to default)
Max Krummenachereeb16b22016-11-30 19:43:09 +0100991 */
Francesco Dolcini1fb07132022-06-24 11:52:19 +0200992 writel(0x010E0101, &ccm->ccosr);
Max Krummenachereeb16b22016-11-30 19:43:09 +0100993}
994
Max Krummenachereeb16b22016-11-30 19:43:09 +0100995static void ddr_init(int *table, int size)
996{
997 int i;
998
999 for (i = 0; i < size / 2 ; i++)
1000 writel(table[2 * i + 1], table[2 * i]);
1001}
1002
Francesco Dolcinie1e30b22021-08-31 11:46:05 +02001003/* Perform DDR DRAM calibration */
1004static void spl_dram_perform_cal(u8 dsize)
1005{
1006#ifdef CONFIG_MX6_DDRCAL
1007 int err;
1008 struct mx6_ddr_sysinfo ddr_sysinfo = {
1009 .dsize = dsize,
1010 };
1011
1012 err = mmdc_do_write_level_calibration(&ddr_sysinfo);
1013 if (err)
1014 printf("error %d from write level calibration\n", err);
1015 err = mmdc_do_dqs_calibration(&ddr_sysinfo);
1016 if (err)
1017 printf("error %d from dqs calibration\n", err);
1018#endif
1019}
1020
Max Krummenachereeb16b22016-11-30 19:43:09 +01001021static void spl_dram_init(void)
1022{
1023 int minc, maxc;
Francesco Dolcinie1e30b22021-08-31 11:46:05 +02001024 u8 dsize = 2;
Max Krummenachereeb16b22016-11-30 19:43:09 +01001025
1026 switch (get_cpu_temp_grade(&minc, &maxc)) {
1027 case TEMP_COMMERCIAL:
1028 case TEMP_EXTCOMMERCIAL:
1029 if (is_cpu_type(MXC_CPU_MX6DL)) {
1030 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1031 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1032 } else {
1033 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
Francesco Dolcinie1e30b22021-08-31 11:46:05 +02001034 dsize = 1;
Max Krummenachereeb16b22016-11-30 19:43:09 +01001035 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1036 }
1037 break;
1038 case TEMP_INDUSTRIAL:
1039 case TEMP_AUTOMOTIVE:
1040 default:
1041 if (is_cpu_type(MXC_CPU_MX6DL)) {
Max Krummenacherc1ce7cb2019-02-08 18:42:17 +01001042 puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
Max Krummenachereeb16b22016-11-30 19:43:09 +01001043 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1044 } else {
1045 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
Francesco Dolcinie1e30b22021-08-31 11:46:05 +02001046 dsize = 1;
Max Krummenachereeb16b22016-11-30 19:43:09 +01001047 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1048 }
1049 break;
1050 };
1051 udelay(100);
Francesco Dolcinie1e30b22021-08-31 11:46:05 +02001052 spl_dram_perform_cal(dsize);
Max Krummenachereeb16b22016-11-30 19:43:09 +01001053}
1054
Gerard Salvatella7fba5092019-02-08 18:42:28 +01001055static iomux_v3_cfg_t const gpio_reset_pad[] = {
1056 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1057 MUX_MODE_SION
1058#define GPIO_NRESET IMX_GPIO_NR(6, 27)
1059};
1060
1061#define IMX_RESET_CAUSE_POR 0x00011
1062static void nreset_out(void)
1063{
1064 int reset_cause = get_imx_reset_cause();
1065
1066 if (reset_cause != IMX_RESET_CAUSE_POR) {
1067 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1068 ARRAY_SIZE(gpio_reset_pad));
1069 gpio_direction_output(GPIO_NRESET, 1);
1070 udelay(100);
1071 gpio_direction_output(GPIO_NRESET, 0);
1072 }
1073}
1074
Max Krummenachereeb16b22016-11-30 19:43:09 +01001075void board_init_f(ulong dummy)
1076{
1077 /* setup AIPS and disable watchdog */
1078 arch_cpu_init();
1079
1080 ccgr_init();
1081 gpr_init();
1082
Marcel Ziswilerc882cfb2019-02-08 18:42:12 +01001083 /* iomux */
Max Krummenachereeb16b22016-11-30 19:43:09 +01001084 board_early_init_f();
1085
1086 /* setup GP timer */
1087 timer_init();
1088
1089 /* UART clocks enabled and gd valid - init serial console */
1090 preloader_console_init();
1091
1092 /* Make sure we use dte mode */
1093 setup_dtemode_uart();
1094
1095 /* DDR initialization */
1096 spl_dram_init();
1097
1098 /* Clear the BSS. */
1099 memset(__bss_start, 0, __bss_end - __bss_start);
1100
Gerard Salvatella7fba5092019-02-08 18:42:28 +01001101 /* Assert nReset_Out */
1102 nreset_out();
1103
Max Krummenachereeb16b22016-11-30 19:43:09 +01001104 /* load/boot image from boot device */
1105 board_init_r(NULL, 0);
1106}
1107
Ming Liuc5c904c2021-07-23 09:39:48 +03001108#ifdef CONFIG_SPL_LOAD_FIT
1109int board_fit_config_name_match(const char *name)
1110{
1111 if (!strcmp(name, "imx6-colibri"))
1112 return 0;
1113
1114 return -1;
1115}
1116#endif
1117
Harald Seiler6f14d5f2020-12-15 16:47:52 +01001118void reset_cpu(void)
Max Krummenachereeb16b22016-11-30 19:43:09 +01001119{
1120}
1121
Marcel Ziswiler3e43a502019-02-08 18:42:10 +01001122#endif /* CONFIG_SPL_BUILD */
Max Krummenachereeb16b22016-11-30 19:43:09 +01001123
Simon Glassb75b15b2020-12-03 16:55:23 -07001124static struct mxc_serial_plat mxc_serial_plat = {
Max Krummenachereeb16b22016-11-30 19:43:09 +01001125 .reg = (struct mxc_uart *)UART1_BASE,
1126 .use_dte = true,
1127};
1128
Simon Glass1d8364a2020-12-28 20:34:54 -07001129U_BOOT_DRVINFO(mxc_serial) = {
Max Krummenachereeb16b22016-11-30 19:43:09 +01001130 .name = "serial_mxc",
Simon Glass71fa5b42020-12-03 16:55:18 -07001131 .plat = &mxc_serial_plat,
Max Krummenachereeb16b22016-11-30 19:43:09 +01001132};