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git01.mediatek.com / filogic / uboot / d42dec0657f9d484d779526e3bd821ef5a7f871f / . / configs / evb-rk3288_defconfig
blob: 14a1d4cf332233a38b679ad06864bfc9035acbe6 [file] [log] [blame]
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
3CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]4CONFIG_SYS_ARCH_TIMER=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]5CONFIG_ARCH_ROCKCHIP=y
Kever Yang6979acf2019-07-09 21:58:46 +0800[diff] [blame]6CONFIG_SYS_TEXT_BASE=0x01000000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=2
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]10CONFIG_ROCKCHIP_RK3288=y
11CONFIG_TARGET_EVB_RK3288=y
Kever Yangab404872019-12-05 18:11:53 +0800[diff] [blame]12CONFIG_SPL_STACK_R_ADDR=0x04000000
Simon Glassa8f0c942019-09-25 08:56:28 -0600[diff] [blame]13CONFIG_SPL_SIZE_LIMIT=0x4b000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]14CONFIG_DEBUG_UART_BASE=0xff690000
15CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]16CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]17CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]18# CONFIG_ANDROID_BOOT_IMAGE is not set
Kever Yange8e1cbc2019-12-05 18:11:55 +0800[diff] [blame]19CONFIG_FIT=y
20CONFIG_FIT_VERBOSE=y
21CONFIG_SPL_LOAD_FIT=y
Simon Glass6a50cd12020-07-19 13:56:12 -0600[diff] [blame]22# CONFIG_USE_SPL_FIT_GENERATOR is not set
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]23CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]24CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]25CONFIG_SILENT_CONSOLE=y
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]26CONFIG_DISPLAY_BOARDINFO_LATE=y
Kever Yang263851d2019-09-18 17:56:42 +0800[diff] [blame]27CONFIG_SPL_STACK_R=y
Kever Yangab404872019-12-05 18:11:53 +0800[diff] [blame]28CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
Patrick Delaunaya7ca4802021-09-02 11:56:16 +0200[diff] [blame]29CONFIG_SPL_OPTEE_IMAGE=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]30CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]31CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]32CONFIG_CMD_I2C=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]33CONFIG_CMD_MMC=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]34CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]35CONFIG_CMD_USB=y
Urja Rannikko17dd9d32019-05-13 13:51:04 +0000[diff] [blame]36CONFIG_CMD_USB_MASS_STORAGE=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]37# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]38CONFIG_CMD_CACHE=y
39CONFIG_CMD_TIME=y
40CONFIG_CMD_PMIC=y
41CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]42# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]43# CONFIG_SPL_EFI_PARTITION is not set
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]44CONFIG_SPL_OF_CONTROL=y
45CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]46CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]47CONFIG_SYS_RELOC_GD_ENV_ADDR=y
David Wu255f68e2018-01-13 13:53:55 +0800[diff] [blame]48CONFIG_NET_RANDOM_ETHADDR=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]49CONFIG_REGMAP=y
50CONFIG_SPL_REGMAP=y
51CONFIG_SYSCON=y
52CONFIG_SPL_SYSCON=y
53CONFIG_CLK=y
54CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]55CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]56CONFIG_ROCKCHIP_GPIO=y
57CONFIG_SYS_I2C_ROCKCHIP=y
58CONFIG_LED=y
59CONFIG_LED_GPIO=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]60CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]61CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]62CONFIG_MTD=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]63CONFIG_SF_DEFAULT_SPEED=20000000
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]64CONFIG_DM_ETH=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]65CONFIG_ETH_DESIGNWARE=y
66CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]67CONFIG_PINCTRL=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]68CONFIG_SPL_PINCTRL=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]69CONFIG_DM_PMIC=y
70CONFIG_PMIC_ACT8846=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]71CONFIG_REGULATOR_ACT8846=y
72CONFIG_DM_REGULATOR_FIXED=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]73CONFIG_PWM_ROCKCHIP=y
74CONFIG_RAM=y
75CONFIG_SPL_RAM=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]76CONFIG_DEBUG_UART_SHIFT=2
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]77CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]78CONFIG_USB=y
Tom Rini6c3798f2018-02-10 20:27:45 -0500[diff] [blame]79CONFIG_USB_DWC2=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]80CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]81CONFIG_USB_GADGET=y
82CONFIG_USB_GADGET_DWC2_OTG=y
eric.gao@rock-chips.com9f127162017-06-21 11:22:03 +0800[diff] [blame]83CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]84# CONFIG_VIDEO_BPP8 is not set
eric.gao@rock-chips.com9f127162017-06-21 11:22:03 +0800[diff] [blame]85CONFIG_DISPLAY=y
86CONFIG_VIDEO_ROCKCHIP=y
87CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
88CONFIG_DISPLAY_ROCKCHIP_MIPI=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]89CONFIG_CMD_DHRYSTONE=y
90CONFIG_ERRNO_STR=y