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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / x86 / dts / qemu-x86_i440fx.dts
blob: 3bb2f121de37226082b2b76960a755c3ec3f2598 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]2/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]4 */
5
6/dts-v1/;
7
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]8#include <dt-bindings/interrupt-router/intel-irq.h>
9
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]10/include/ "skeleton.dtsi"
11/include/ "serial.dtsi"
Bin Meng7ca73742015-11-12 05:33:06 -0800[diff] [blame]12/include/ "keyboard.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -0700[diff] [blame]13/include/ "reset.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]14/include/ "rtc.dtsi"
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]15
Bin Meng8967f632021-07-28 12:00:23 +0800[diff] [blame]16#include "tsc_timer.dtsi"
Simon Glassbee77f62020-11-05 06:32:17 -0700[diff] [blame]17#include "smbios.dtsi"
18
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]19/ {
Bin Meng000883b2015-06-03 09:20:04 +0800[diff] [blame]20 model = "QEMU x86 (I440FX)";
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]21 compatible = "qemu,x86";
22
23 config {
24 silent_console = <0>;
25 };
26
27 chosen {
28 stdout-path = "/serial";
29 };
30
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]34 bootph-all;
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]35
36 cpu@0 {
37 device_type = "cpu";
Miao Yan4336af62016-01-07 01:32:01 -0800[diff] [blame]38 compatible = "cpu-qemu";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]39 bootph-all;
Bin Meng354dcdd2015-07-22 01:21:13 -0700[diff] [blame]40 reg = <0>;
41 intel,apic-id = <0>;
42 };
43 };
44
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]45 pci {
46 compatible = "pci-x86";
47 #address-cells = <3>;
48 #size-cells = <2>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]49 bootph-all;
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]50 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
51 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
52 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]53
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]54 pch@1,0 {
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]55 reg = <0x00000800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]56 compatible = "intel,pch7";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]57 bootph-all;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]58
59 irq-router {
60 compatible = "intel,irq-router";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]61 bootph-all;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]62 intel,pirq-config = "pci";
63 intel,pirq-link = <0x60 4>;
64 intel,pirq-mask = <0x0e40>;
65 intel,pirq-routing = <
66 /* PIIX UHCI */
67 PCI_BDF(0, 1, 2) INTD PIRQD
68 /* e1000 NIC */
69 PCI_BDF(0, 3, 0) INTA PIRQC
70 >;
71 };
Bin Mengef37e7b2015-06-03 09:20:06 +0800[diff] [blame]72 };
Bin Meng2229c4c2015-05-07 21:34:08 +0800[diff] [blame]73 };
74
75};