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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / stm32mp15-ddr.dtsi
blob: 48b0828828fe203830269efc51a60070ba487039 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]2/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]4 */
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]5#include <linux/stringify.h>
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]6
Patrick Delaunaydb8bb352022-09-21 09:37:13 +0200[diff] [blame]7#ifdef CONFIG_SPL
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]8&ddr {
Patrick Delaunaydb8bb352022-09-21 09:37:13 +0200[diff] [blame]9 clocks = <&rcc AXIDCG>,
10 <&rcc DDRC1>,
11 <&rcc DDRC2>,
12 <&rcc DDRPHYC>,
13 <&rcc DDRCAPB>,
14 <&rcc DDRPHYCAPB>;
15
16 clock-names = "axidcg",
17 "ddrc1",
18 "ddrc2",
19 "ddrphyc",
20 "ddrcapb",
21 "ddrphycapb";
22
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]23 config-DDR_MEM_COMPATIBLE {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]24 bootph-all;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]25
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]26 compatible = __stringify(st,DDR_MEM_COMPATIBLE);
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]27
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]28 st,mem-name = DDR_MEM_NAME;
29 st,mem-speed = <DDR_MEM_SPEED>;
30 st,mem-size = <DDR_MEM_SIZE>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]31
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]32 st,ctl-reg = <
33 DDR_MSTR
34 DDR_MRCTRL0
35 DDR_MRCTRL1
36 DDR_DERATEEN
37 DDR_DERATEINT
38 DDR_PWRCTL
39 DDR_PWRTMG
40 DDR_HWLPCTL
41 DDR_RFSHCTL0
42 DDR_RFSHCTL3
43 DDR_CRCPARCTL0
44 DDR_ZQCTL0
45 DDR_DFITMG0
46 DDR_DFITMG1
47 DDR_DFILPCFG0
48 DDR_DFIUPD0
49 DDR_DFIUPD1
50 DDR_DFIUPD2
51 DDR_DFIPHYMSTR
52 DDR_ODTMAP
53 DDR_DBG0
54 DDR_DBG1
55 DDR_DBGCMD
56 DDR_POISONCFG
57 DDR_PCCFG
58 >;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]59
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]60 st,ctl-timing = <
61 DDR_RFSHTMG
62 DDR_DRAMTMG0
63 DDR_DRAMTMG1
64 DDR_DRAMTMG2
65 DDR_DRAMTMG3
66 DDR_DRAMTMG4
67 DDR_DRAMTMG5
68 DDR_DRAMTMG6
69 DDR_DRAMTMG7
70 DDR_DRAMTMG8
71 DDR_DRAMTMG14
72 DDR_ODTCFG
73 >;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]74
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]75 st,ctl-map = <
76 DDR_ADDRMAP1
77 DDR_ADDRMAP2
78 DDR_ADDRMAP3
79 DDR_ADDRMAP4
80 DDR_ADDRMAP5
81 DDR_ADDRMAP6
82 DDR_ADDRMAP9
83 DDR_ADDRMAP10
84 DDR_ADDRMAP11
85 >;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]86
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]87 st,ctl-perf = <
88 DDR_SCHED
89 DDR_SCHED1
90 DDR_PERFHPR1
91 DDR_PERFLPR1
92 DDR_PERFWR1
93 DDR_PCFGR_0
94 DDR_PCFGW_0
95 DDR_PCFGQOS0_0
96 DDR_PCFGQOS1_0
97 DDR_PCFGWQOS0_0
98 DDR_PCFGWQOS1_0
99 DDR_PCFGR_1
100 DDR_PCFGW_1
101 DDR_PCFGQOS0_1
102 DDR_PCFGQOS1_1
103 DDR_PCFGWQOS0_1
104 DDR_PCFGWQOS1_1
105 >;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]106
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]107 st,phy-reg = <
108 DDR_PGCR
109 DDR_ACIOCR
110 DDR_DXCCR
111 DDR_DSGCR
112 DDR_DCR
113 DDR_ODTCR
114 DDR_ZQ0CR1
115 DDR_DX0GCR
116 DDR_DX1GCR
117 DDR_DX2GCR
118 DDR_DX3GCR
119 >;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]120
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]121 st,phy-timing = <
122 DDR_PTR0
123 DDR_PTR1
124 DDR_PTR2
125 DDR_DTPR0
126 DDR_DTPR1
127 DDR_DTPR2
128 DDR_MR0
129 DDR_MR1
130 DDR_MR2
131 DDR_MR3
132 >;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]133
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]134 status = "okay";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]135 };
136};
Patrick Delaunaydb8bb352022-09-21 09:37:13 +0200[diff] [blame]137#endif
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]138
139#undef DDR_MEM_COMPATIBLE
140#undef DDR_MEM_NAME
141#undef DDR_MEM_SPEED
142#undef DDR_MEM_SIZE
143
144#undef DDR_MSTR
145#undef DDR_MRCTRL0
146#undef DDR_MRCTRL1
147#undef DDR_DERATEEN
148#undef DDR_DERATEINT
149#undef DDR_PWRCTL
150#undef DDR_PWRTMG
151#undef DDR_HWLPCTL
152#undef DDR_RFSHCTL0
153#undef DDR_RFSHCTL3
154#undef DDR_RFSHTMG
155#undef DDR_CRCPARCTL0
156#undef DDR_DRAMTMG0
157#undef DDR_DRAMTMG1
158#undef DDR_DRAMTMG2
159#undef DDR_DRAMTMG3
160#undef DDR_DRAMTMG4
161#undef DDR_DRAMTMG5
162#undef DDR_DRAMTMG6
163#undef DDR_DRAMTMG7
164#undef DDR_DRAMTMG8
165#undef DDR_DRAMTMG14
166#undef DDR_ZQCTL0
167#undef DDR_DFITMG0
168#undef DDR_DFITMG1
169#undef DDR_DFILPCFG0
170#undef DDR_DFIUPD0
171#undef DDR_DFIUPD1
172#undef DDR_DFIUPD2
173#undef DDR_DFIPHYMSTR
174#undef DDR_ADDRMAP1
175#undef DDR_ADDRMAP2
176#undef DDR_ADDRMAP3
177#undef DDR_ADDRMAP4
178#undef DDR_ADDRMAP5
179#undef DDR_ADDRMAP6
180#undef DDR_ADDRMAP9
181#undef DDR_ADDRMAP10
182#undef DDR_ADDRMAP11
183#undef DDR_ODTCFG
184#undef DDR_ODTMAP
185#undef DDR_SCHED
186#undef DDR_SCHED1
187#undef DDR_PERFHPR1
188#undef DDR_PERFLPR1
189#undef DDR_PERFWR1
190#undef DDR_DBG0
191#undef DDR_DBG1
192#undef DDR_DBGCMD
193#undef DDR_POISONCFG
194#undef DDR_PCCFG
195#undef DDR_PCFGR_0
196#undef DDR_PCFGW_0
197#undef DDR_PCFGQOS0_0
198#undef DDR_PCFGQOS1_0
199#undef DDR_PCFGWQOS0_0
200#undef DDR_PCFGWQOS1_0
201#undef DDR_PCFGR_1
202#undef DDR_PCFGW_1
203#undef DDR_PCFGQOS0_1
204#undef DDR_PCFGQOS1_1
205#undef DDR_PCFGWQOS0_1
206#undef DDR_PCFGWQOS1_1
207#undef DDR_PGCR
208#undef DDR_PTR0
209#undef DDR_PTR1
210#undef DDR_PTR2
211#undef DDR_ACIOCR
212#undef DDR_DXCCR
213#undef DDR_DSGCR
214#undef DDR_DCR
215#undef DDR_DTPR0
216#undef DDR_DTPR1
217#undef DDR_DTPR2
218#undef DDR_MR0
219#undef DDR_MR1
220#undef DDR_MR2
221#undef DDR_MR3
222#undef DDR_ODTCR
223#undef DDR_ZQ0CR1
224#undef DDR_DX0GCR
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]225#undef DDR_DX1GCR
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]226#undef DDR_DX2GCR
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]227#undef DDR_DX3GCR