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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / sama5d3.dtsi
blob: 4c03a302ec793a75db0afc3661f7eb25cfd8e244 [file] [log] [blame]
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include "skeleton.dtsi"
12#include <dt-bindings/dma/at91.h>
13#include <dt-bindings/pinctrl/at91.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/clock/at91.h>
17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 serial5 = &uart0;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 i2c0 = &i2c0;
37 i2c1 = &i2c1;
38 i2c2 = &i2c2;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a5";
49 reg = <0x0>;
50 };
51 };
52
53 pmu {
54 compatible = "arm,cortex-a5-pmu";
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
56 };
57
58 memory {
59 reg = <0x20000000 0x8000000>;
60 };
61
62 clocks {
63 slow_xtal: slow_xtal {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 main_xtal: main_xtal {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <0>;
73 };
74
75 adc_op_clk: adc_op_clk{
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <1000000>;
79 };
80 };
81
82 sram: sram@00300000 {
83 compatible = "mmio-sram";
84 reg = <0x00300000 0x20000>;
85 };
86
87 ahb {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]92 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]93
94 apb {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]99 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]100
101 mmc0: mmc@f0000000 {
102 compatible = "atmel,hsmci";
103 reg = <0xf0000000 0x600>;
104 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
105 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
106 dma-names = "rxtx";
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
109 status = "disabled";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 clocks = <&mci0_clk>;
113 clock-names = "mci_clk";
114 };
115
116 spi0: spi@f0004000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "atmel,at91rm9200-spi";
120 reg = <0xf0004000 0x100>;
121 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
122 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
123 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
124 dma-names = "tx", "rx";
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_spi0>;
127 clocks = <&spi0_clk>;
128 clock-names = "spi_clk";
129 status = "disabled";
130 };
131
132 ssc0: ssc@f0008000 {
133 compatible = "atmel,at91sam9g45-ssc";
134 reg = <0xf0008000 0x4000>;
135 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
136 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
137 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
138 dma-names = "tx", "rx";
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
141 clocks = <&ssc0_clk>;
142 clock-names = "pclk";
143 status = "disabled";
144 };
145
146 tcb0: timer@f0010000 {
147 compatible = "atmel,at91sam9x5-tcb";
148 reg = <0xf0010000 0x100>;
149 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
150 clocks = <&tcb0_clk>, <&clk32k>;
151 clock-names = "t0_clk", "slow_clk";
152 };
153
154 i2c0: i2c@f0014000 {
155 compatible = "atmel,at91sam9x5-i2c";
156 reg = <0xf0014000 0x4000>;
157 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
158 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
159 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_i2c0>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 clocks = <&twi0_clk>;
166 status = "disabled";
167 };
168
169 i2c1: i2c@f0018000 {
170 compatible = "atmel,at91sam9x5-i2c";
171 reg = <0xf0018000 0x4000>;
172 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
173 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
174 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
175 dma-names = "tx", "rx";
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_i2c1>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 clocks = <&twi1_clk>;
181 status = "disabled";
182 };
183
184 usart0: serial@f001c000 {
185 compatible = "atmel,at91sam9260-usart";
186 reg = <0xf001c000 0x100>;
187 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
188 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
189 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
190 dma-names = "tx", "rx";
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usart0>;
193 clocks = <&usart0_clk>;
194 clock-names = "usart";
195 status = "disabled";
196 };
197
198 usart1: serial@f0020000 {
199 compatible = "atmel,at91sam9260-usart";
200 reg = <0xf0020000 0x100>;
201 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
202 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
203 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
204 dma-names = "tx", "rx";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_usart1>;
207 clocks = <&usart1_clk>;
208 clock-names = "usart";
209 status = "disabled";
210 };
211
212 uart0: serial@f0024000 {
213 compatible = "atmel,at91sam9260-usart";
214 reg = <0xf0024000 0x100>;
215 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart0>;
218 clocks = <&uart0_clk>;
219 clock-names = "usart";
220 status = "disabled";
221 };
222
223 pwm0: pwm@f002c000 {
224 compatible = "atmel,sama5d3-pwm";
225 reg = <0xf002c000 0x300>;
226 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
227 #pwm-cells = <3>;
228 clocks = <&pwm_clk>;
229 status = "disabled";
230 };
231
232 isi: isi@f0034000 {
233 compatible = "atmel,at91sam9g45-isi";
234 reg = <0xf0034000 0x4000>;
235 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_isi_data_0_7>;
238 clocks = <&isi_clk>;
239 clock-names = "isi_clk";
240 status = "disabled";
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]241 };
242
243 sfr: sfr@f0038000 {
244 compatible = "atmel,sama5d3-sfr", "syscon";
245 reg = <0xf0038000 0x60>;
246 };
247
248 mmc1: mmc@f8000000 {
249 compatible = "atmel,hsmci";
250 reg = <0xf8000000 0x600>;
251 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
252 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
253 dma-names = "rxtx";
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
256 status = "disabled";
257 #address-cells = <1>;
258 #size-cells = <0>;
259 clocks = <&mci1_clk>;
260 clock-names = "mci_clk";
261 };
262
263 spi1: spi@f8008000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "atmel,at91rm9200-spi";
267 reg = <0xf8008000 0x100>;
268 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
269 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
270 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
271 dma-names = "tx", "rx";
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_spi1>;
274 clocks = <&spi1_clk>;
275 clock-names = "spi_clk";
276 status = "disabled";
277 };
278
279 ssc1: ssc@f800c000 {
280 compatible = "atmel,at91sam9g45-ssc";
281 reg = <0xf800c000 0x4000>;
282 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
283 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
284 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
285 dma-names = "tx", "rx";
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
288 clocks = <&ssc1_clk>;
289 clock-names = "pclk";
290 status = "disabled";
291 };
292
293 adc0: adc@f8018000 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "atmel,at91sam9x5-adc";
297 reg = <0xf8018000 0x100>;
298 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
299 pinctrl-names = "default";
300 pinctrl-0 = <
301 &pinctrl_adc0_adtrg
302 &pinctrl_adc0_ad0
303 &pinctrl_adc0_ad1
304 &pinctrl_adc0_ad2
305 &pinctrl_adc0_ad3
306 &pinctrl_adc0_ad4
307 &pinctrl_adc0_ad5
308 &pinctrl_adc0_ad6
309 &pinctrl_adc0_ad7
310 &pinctrl_adc0_ad8
311 &pinctrl_adc0_ad9
312 &pinctrl_adc0_ad10
313 &pinctrl_adc0_ad11
314 >;
315 clocks = <&adc_clk>,
316 <&adc_op_clk>;
317 clock-names = "adc_clk", "adc_op_clk";
318 atmel,adc-channels-used = <0xfff>;
319 atmel,adc-startup-time = <40>;
320 atmel,adc-use-external-triggers;
321 atmel,adc-vref = <3000>;
322 atmel,adc-res = <10 12>;
323 atmel,adc-sample-hold-time = <11>;
324 atmel,adc-res-names = "lowres", "highres";
325 status = "disabled";
326
327 trigger@0 {
328 reg = <0>;
329 trigger-name = "external-rising";
330 trigger-value = <0x1>;
331 trigger-external;
332 };
333 trigger@1 {
334 reg = <1>;
335 trigger-name = "external-falling";
336 trigger-value = <0x2>;
337 trigger-external;
338 };
339 trigger@2 {
340 reg = <2>;
341 trigger-name = "external-any";
342 trigger-value = <0x3>;
343 trigger-external;
344 };
345 trigger@3 {
346 reg = <3>;
347 trigger-name = "continuous";
348 trigger-value = <0x6>;
349 };
350 };
351
352 i2c2: i2c@f801c000 {
353 compatible = "atmel,at91sam9x5-i2c";
354 reg = <0xf801c000 0x4000>;
355 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
357 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_i2c2>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clocks = <&twi2_clk>;
364 status = "disabled";
365 };
366
367 usart2: serial@f8020000 {
368 compatible = "atmel,at91sam9260-usart";
369 reg = <0xf8020000 0x100>;
370 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
371 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
372 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
373 dma-names = "tx", "rx";
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_usart2>;
376 clocks = <&usart2_clk>;
377 clock-names = "usart";
378 status = "disabled";
379 };
380
381 usart3: serial@f8024000 {
382 compatible = "atmel,at91sam9260-usart";
383 reg = <0xf8024000 0x100>;
384 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
385 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
386 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
387 dma-names = "tx", "rx";
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_usart3>;
390 clocks = <&usart3_clk>;
391 clock-names = "usart";
392 status = "disabled";
393 };
394
395 sha@f8034000 {
396 compatible = "atmel,at91sam9g46-sha";
397 reg = <0xf8034000 0x100>;
398 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
399 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
400 dma-names = "tx";
401 clocks = <&sha_clk>;
402 clock-names = "sha_clk";
403 };
404
405 aes@f8038000 {
406 compatible = "atmel,at91sam9g46-aes";
407 reg = <0xf8038000 0x100>;
408 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
409 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
410 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
411 dma-names = "tx", "rx";
412 clocks = <&aes_clk>;
413 clock-names = "aes_clk";
414 };
415
416 tdes@f803c000 {
417 compatible = "atmel,at91sam9g46-tdes";
418 reg = <0xf803c000 0x100>;
419 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
420 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
421 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
422 dma-names = "tx", "rx";
423 clocks = <&tdes_clk>;
424 clock-names = "tdes_clk";
425 };
426
427 trng@f8040000 {
428 compatible = "atmel,at91sam9g45-trng";
429 reg = <0xf8040000 0x100>;
430 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
431 clocks = <&trng_clk>;
432 };
433
434 dma0: dma-controller@ffffe600 {
435 compatible = "atmel,at91sam9g45-dma";
436 reg = <0xffffe600 0x200>;
437 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
438 #dma-cells = <2>;
439 clocks = <&dma0_clk>;
440 clock-names = "dma_clk";
441 };
442
443 dma1: dma-controller@ffffe800 {
444 compatible = "atmel,at91sam9g45-dma";
445 reg = <0xffffe800 0x200>;
446 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
447 #dma-cells = <2>;
448 clocks = <&dma1_clk>;
449 clock-names = "dma_clk";
450 };
451
452 ramc0: ramc@ffffea00 {
453 compatible = "atmel,sama5d3-ddramc";
454 reg = <0xffffea00 0x200>;
455 clocks = <&ddrck>, <&mpddr_clk>;
456 clock-names = "ddrck", "mpddr";
457 };
458
459 dbgu: serial@ffffee00 {
460 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
461 reg = <0xffffee00 0x200>;
462 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
463 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
464 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
465 dma-names = "tx", "rx";
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_dbgu>;
468 clocks = <&dbgu_clk>;
469 clock-names = "usart";
470 status = "disabled";
471 };
472
473 aic: interrupt-controller@fffff000 {
474 #interrupt-cells = <3>;
475 compatible = "atmel,sama5d3-aic";
476 interrupt-controller;
477 reg = <0xfffff000 0x200>;
478 atmel,external-irqs = <47>;
479 };
480
481 pinctrl@fffff200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]482 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]483 #address-cells = <1>;
484 #size-cells = <1>;
485 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
486 ranges = <0xfffff200 0xfffff200 0xa00>;
487 atmel,mux-mask = <
488 /* A B C */
489 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
490 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
491 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
492 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
493 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
494 >;
495 reg = <0xfffff200 0x100 /* pioA */
496 0xfffff400 0x100 /* pioB */
497 0xfffff600 0x100 /* pioC */
498 0xfffff800 0x100 /* pioD */
499 0xfffffa00 0x100 /* pioE */
500 >;
501
502 /* shared pinctrl settings */
503 adc0 {
504 pinctrl_adc0_adtrg: adc0_adtrg {
505 atmel,pins =
506 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
507 };
508 pinctrl_adc0_ad0: adc0_ad0 {
509 atmel,pins =
510 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
511 };
512 pinctrl_adc0_ad1: adc0_ad1 {
513 atmel,pins =
514 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
515 };
516 pinctrl_adc0_ad2: adc0_ad2 {
517 atmel,pins =
518 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
519 };
520 pinctrl_adc0_ad3: adc0_ad3 {
521 atmel,pins =
522 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
523 };
524 pinctrl_adc0_ad4: adc0_ad4 {
525 atmel,pins =
526 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
527 };
528 pinctrl_adc0_ad5: adc0_ad5 {
529 atmel,pins =
530 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
531 };
532 pinctrl_adc0_ad6: adc0_ad6 {
533 atmel,pins =
534 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
535 };
536 pinctrl_adc0_ad7: adc0_ad7 {
537 atmel,pins =
538 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
539 };
540 pinctrl_adc0_ad8: adc0_ad8 {
541 atmel,pins =
542 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
543 };
544 pinctrl_adc0_ad9: adc0_ad9 {
545 atmel,pins =
546 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
547 };
548 pinctrl_adc0_ad10: adc0_ad10 {
549 atmel,pins =
550 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
551 };
552 pinctrl_adc0_ad11: adc0_ad11 {
553 atmel,pins =
554 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
555 };
556 };
557
558 dbgu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]559 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]560 pinctrl_dbgu: dbgu-0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]561 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]562 atmel,pins =
563 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
564 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
565 };
566 };
567
568 i2c0 {
569 pinctrl_i2c0: i2c0-0 {
570 atmel,pins =
571 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
572 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
573 };
574 };
575
576 i2c1 {
577 pinctrl_i2c1: i2c1-0 {
578 atmel,pins =
579 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
580 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
581 };
582 };
583
584 i2c2 {
585 pinctrl_i2c2: i2c2-0 {
586 atmel,pins =
587 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
588 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
589 };
590 };
591
592 isi {
593 pinctrl_isi_data_0_7: isi-0-data-0-7 {
594 atmel,pins =
595 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
596 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
597 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
598 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
599 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
600 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
601 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
602 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
603 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
604 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
605 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
606 };
607
608 pinctrl_isi_data_8_9: isi-0-data-8-9 {
609 atmel,pins =
610 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
611 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
612 };
613
614 pinctrl_isi_data_10_11: isi-0-data-10-11 {
615 atmel,pins =
616 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
617 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
618 };
619 };
620
621 mmc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]622 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]623 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]624 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]625 atmel,pins =
626 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
627 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
628 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
629 };
630 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]631 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]632 atmel,pins =
633 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
634 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
635 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
636 };
637 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]638 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]639 atmel,pins =
640 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
641 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
642 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
643 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
644 };
645 };
646
647 mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]648 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]649 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]650 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]651 atmel,pins =
652 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
653 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
654 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655 };
656 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]657 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]658 atmel,pins =
659 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
660 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
661 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
662 };
663 };
664
665 nand0 {
666 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
667 atmel,pins =
668 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
669 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
670 };
671 };
672
673 pwm0 {
674 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
675 atmel,pins =
676 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
677 };
678 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
679 atmel,pins =
680 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
681 };
682 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
683 atmel,pins =
684 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
685 };
686 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
687 atmel,pins =
688 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
689 };
690
691 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
692 atmel,pins =
693 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
694 };
695 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
696 atmel,pins =
697 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
698 };
699 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
700 atmel,pins =
701 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
702 };
703 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
704 atmel,pins =
705 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
706 };
707 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
708 atmel,pins =
709 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
710 };
711 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
712 atmel,pins =
713 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
714 };
715
716 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
717 atmel,pins =
718 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
719 };
720 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
721 atmel,pins =
722 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
723 };
724 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
725 atmel,pins =
726 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
727 };
728 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
729 atmel,pins =
730 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
731 };
732
733 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
734 atmel,pins =
735 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
736 };
737 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
738 atmel,pins =
739 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
740 };
741 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
742 atmel,pins =
743 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
744 };
745 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
746 atmel,pins =
747 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
748 };
749 };
750
751 spi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]752 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]753 pinctrl_spi0: spi0-0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]754 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]755 atmel,pins =
756 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
757 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
758 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
759 };
760 };
761
762 spi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]763 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]764 pinctrl_spi1: spi1-0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]765 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]766 atmel,pins =
767 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
768 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
769 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
770 };
771 };
772
773 ssc0 {
774 pinctrl_ssc0_tx: ssc0_tx {
775 atmel,pins =
776 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
777 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
778 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
779 };
780
781 pinctrl_ssc0_rx: ssc0_rx {
782 atmel,pins =
783 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
784 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
785 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
786 };
787 };
788
789 ssc1 {
790 pinctrl_ssc1_tx: ssc1_tx {
791 atmel,pins =
792 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
793 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
794 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
795 };
796
797 pinctrl_ssc1_rx: ssc1_rx {
798 atmel,pins =
799 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
800 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
801 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
802 };
803 };
804
805 uart0 {
806 pinctrl_uart0: uart0-0 {
807 atmel,pins =
808 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */
809 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */
810 };
811 };
812
813 uart1 {
814 pinctrl_uart1: uart1-0 {
815 atmel,pins =
816 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */
817 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */
818 };
819 };
820
821 usart0 {
822 pinctrl_usart0: usart0-0 {
823 atmel,pins =
824 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
825 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
826 };
827
828 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
829 atmel,pins =
830 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
831 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
832 };
833 };
834
835 usart1 {
836 pinctrl_usart1: usart1-0 {
837 atmel,pins =
838 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
839 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
840 };
841
842 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
843 atmel,pins =
844 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
845 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
846 };
847 };
848
849 usart2 {
850 pinctrl_usart2: usart2-0 {
851 atmel,pins =
852 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
853 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
854 };
855
856 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
857 atmel,pins =
858 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
859 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
860 };
861 };
862
863 usart3 {
864 pinctrl_usart3: usart3-0 {
865 atmel,pins =
866 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
867 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
868 };
869
870 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
871 atmel,pins =
872 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
873 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
874 };
875 };
876 };
877
878 pioA: gpio@fffff200 {
879 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
880 reg = <0xfffff200 0x100>;
881 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
882 #gpio-cells = <2>;
883 gpio-controller;
884 interrupt-controller;
885 #interrupt-cells = <2>;
886 clocks = <&pioA_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]887 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]888 };
889
890 pioB: gpio@fffff400 {
891 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
892 reg = <0xfffff400 0x100>;
893 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
894 #gpio-cells = <2>;
895 gpio-controller;
896 interrupt-controller;
897 #interrupt-cells = <2>;
898 clocks = <&pioB_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]899 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]900 };
901
902 pioC: gpio@fffff600 {
903 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
904 reg = <0xfffff600 0x100>;
905 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
906 #gpio-cells = <2>;
907 gpio-controller;
908 interrupt-controller;
909 #interrupt-cells = <2>;
910 clocks = <&pioC_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]911 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]912 };
913
914 pioD: gpio@fffff800 {
915 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
916 reg = <0xfffff800 0x100>;
917 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
918 #gpio-cells = <2>;
919 gpio-controller;
920 interrupt-controller;
921 #interrupt-cells = <2>;
922 clocks = <&pioD_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]923 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]924 };
925
926 pioE: gpio@fffffa00 {
927 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
928 reg = <0xfffffa00 0x100>;
929 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
930 #gpio-cells = <2>;
931 gpio-controller;
932 interrupt-controller;
933 #interrupt-cells = <2>;
934 clocks = <&pioE_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]935 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]936 };
937
938 pmc: pmc@fffffc00 {
939 compatible = "atmel,sama5d3-pmc", "syscon";
940 reg = <0xfffffc00 0x120>;
941 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
942 interrupt-controller;
943 #address-cells = <1>;
944 #size-cells = <0>;
945 #interrupt-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]946 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]947
948 main_rc_osc: main_rc_osc {
949 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
950 #clock-cells = <0>;
951 interrupt-parent = <&pmc>;
952 interrupts = <AT91_PMC_MOSCRCS>;
953 clock-frequency = <12000000>;
954 clock-accuracy = <50000000>;
955 };
956
957 main_osc: main_osc {
958 compatible = "atmel,at91rm9200-clk-main-osc";
959 #clock-cells = <0>;
960 interrupt-parent = <&pmc>;
961 interrupts = <AT91_PMC_MOSCS>;
962 clocks = <&main_xtal>;
963 };
964
965 main: mainck {
966 compatible = "atmel,at91sam9x5-clk-main";
967 #clock-cells = <0>;
968 interrupt-parent = <&pmc>;
969 interrupts = <AT91_PMC_MOSCSELS>;
970 clocks = <&main_rc_osc &main_osc>;
971 };
972
973 plla: pllack@0 {
974 compatible = "atmel,sama5d3-clk-pll";
975 #clock-cells = <0>;
976 interrupt-parent = <&pmc>;
977 interrupts = <AT91_PMC_LOCKA>;
978 clocks = <&main>;
979 reg = <0>;
980 atmel,clk-input-range = <8000000 50000000>;
981 #atmel,pll-clk-output-range-cells = <4>;
982 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
983 };
984
985 plladiv: plladivck {
986 compatible = "atmel,at91sam9x5-clk-plldiv";
987 #clock-cells = <0>;
988 clocks = <&plla>;
989 };
990
991 utmi: utmick {
992 compatible = "atmel,at91sam9x5-clk-utmi";
993 #clock-cells = <0>;
994 interrupt-parent = <&pmc>;
995 interrupts = <AT91_PMC_LOCKU>;
996 clocks = <&main>;
Wenyou Yang75648fb2017-09-05 18:30:08 +0800[diff] [blame]997 regmap-sfr = <&sfr>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]998 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]999 };
1000
1001 mck: masterck {
1002 compatible = "atmel,at91sam9x5-clk-master";
1003 #clock-cells = <0>;
1004 interrupt-parent = <&pmc>;
1005 interrupts = <AT91_PMC_MCKRDY>;
1006 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
1007 atmel,clk-output-range = <0 166000000>;
1008 atmel,clk-divisors = <1 2 4 3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1009 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1010 };
1011
1012 usb: usbck {
1013 compatible = "atmel,at91sam9x5-clk-usb";
1014 #clock-cells = <0>;
1015 clocks = <&plladiv>, <&utmi>;
1016 };
1017
1018 prog: progck {
1019 compatible = "atmel,at91sam9x5-clk-programmable";
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 interrupt-parent = <&pmc>;
1023 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
1024
1025 prog0: progck@0 {
1026 #clock-cells = <0>;
1027 reg = <0>;
1028 interrupts = <AT91_PMC_PCKRDY(0)>;
1029 };
1030
1031 prog1: progck@1 {
1032 #clock-cells = <0>;
1033 reg = <1>;
1034 interrupts = <AT91_PMC_PCKRDY(1)>;
1035 };
1036
1037 prog2: progck@2 {
1038 #clock-cells = <0>;
1039 reg = <2>;
1040 interrupts = <AT91_PMC_PCKRDY(2)>;
1041 };
1042 };
1043
1044 smd: smdclk {
1045 compatible = "atmel,at91sam9x5-clk-smd";
1046 #clock-cells = <0>;
1047 clocks = <&plladiv>, <&utmi>;
1048 };
1049
1050 systemck {
1051 compatible = "atmel,at91rm9200-clk-system";
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054
1055 ddrck: ddrck@2 {
1056 #clock-cells = <0>;
1057 reg = <2>;
1058 clocks = <&mck>;
1059 };
1060
1061 smdck: smdck@4 {
1062 #clock-cells = <0>;
1063 reg = <4>;
1064 clocks = <&smd>;
1065 };
1066
1067 uhpck: uhpck@6 {
1068 #clock-cells = <0>;
1069 reg = <6>;
1070 clocks = <&usb>;
1071 };
1072
1073 udpck: udpck@7 {
1074 #clock-cells = <0>;
1075 reg = <7>;
1076 clocks = <&usb>;
1077 };
1078
1079 pck0: pck@8 {
1080 #clock-cells = <0>;
1081 reg = <8>;
1082 clocks = <&prog0>;
1083 };
1084
1085 pck1: pck@9 {
1086 #clock-cells = <0>;
1087 reg = <9>;
1088 clocks = <&prog1>;
1089 };
1090
1091 pck2: pck@10 {
1092 #clock-cells = <0>;
1093 reg = <10>;
1094 clocks = <&prog2>;
1095 };
1096 };
1097
1098 periphck {
1099 compatible = "atmel,at91sam9x5-clk-peripheral";
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1103 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1104
1105 dbgu_clk: dbgu_clk@2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1106 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1107 #clock-cells = <0>;
1108 reg = <2>;
1109 };
1110
1111 hsmc_clk: hsmc_clk@5 {
1112 #clock-cells = <0>;
1113 reg = <5>;
1114 };
1115
1116 pioA_clk: pioA_clk@6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1117 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1118 #clock-cells = <0>;
1119 reg = <6>;
1120 };
1121
1122 pioB_clk: pioB_clk@7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1123 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1124 #clock-cells = <0>;
1125 reg = <7>;
1126 };
1127
1128 pioC_clk: pioC_clk@8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1129 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1130 #clock-cells = <0>;
1131 reg = <8>;
1132 };
1133
1134 pioD_clk: pioD_clk@9 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1135 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1136 #clock-cells = <0>;
1137 reg = <9>;
1138 };
1139
1140 pioE_clk: pioE_clk@10 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1141 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1142 #clock-cells = <0>;
1143 reg = <10>;
1144 };
1145
1146 usart0_clk: usart0_clk@12 {
1147 #clock-cells = <0>;
1148 reg = <12>;
1149 atmel,clk-output-range = <0 66000000>;
1150 };
1151
1152 usart1_clk: usart1_clk@13 {
1153 #clock-cells = <0>;
1154 reg = <13>;
1155 atmel,clk-output-range = <0 66000000>;
1156 };
1157
1158 usart2_clk: usart2_clk@14 {
1159 #clock-cells = <0>;
1160 reg = <14>;
1161 atmel,clk-output-range = <0 66000000>;
1162 };
1163
1164 usart3_clk: usart3_clk@15 {
1165 #clock-cells = <0>;
1166 reg = <15>;
1167 atmel,clk-output-range = <0 66000000>;
1168 };
1169
1170 uart0_clk: uart0_clk@16 {
1171 #clock-cells = <0>;
1172 reg = <16>;
1173 atmel,clk-output-range = <0 66000000>;
1174 };
1175
1176 twi0_clk: twi0_clk@18 {
1177 reg = <18>;
1178 #clock-cells = <0>;
1179 atmel,clk-output-range = <0 16625000>;
1180 };
1181
1182 twi1_clk: twi1_clk@19 {
1183 #clock-cells = <0>;
1184 reg = <19>;
1185 atmel,clk-output-range = <0 16625000>;
1186 };
1187
1188 twi2_clk: twi2_clk@20 {
1189 #clock-cells = <0>;
1190 reg = <20>;
1191 atmel,clk-output-range = <0 16625000>;
1192 };
1193
1194 mci0_clk: mci0_clk@21 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1195 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1196 #clock-cells = <0>;
1197 reg = <21>;
1198 };
1199
1200 mci1_clk: mci1_clk@22 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1201 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1202 #clock-cells = <0>;
1203 reg = <22>;
1204 };
1205
1206 spi0_clk: spi0_clk@24 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1207 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1208 #clock-cells = <0>;
1209 reg = <24>;
1210 atmel,clk-output-range = <0 133000000>;
1211 };
1212
1213 spi1_clk: spi1_clk@25 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1214 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1215 #clock-cells = <0>;
1216 reg = <25>;
1217 atmel,clk-output-range = <0 133000000>;
1218 };
1219
1220 tcb0_clk: tcb0_clk@26 {
1221 #clock-cells = <0>;
1222 reg = <26>;
1223 atmel,clk-output-range = <0 133000000>;
1224 };
1225
1226 pwm_clk: pwm_clk@28 {
1227 #clock-cells = <0>;
1228 reg = <28>;
1229 };
1230
1231 adc_clk: adc_clk@29 {
1232 #clock-cells = <0>;
1233 reg = <29>;
1234 atmel,clk-output-range = <0 66000000>;
1235 };
1236
1237 dma0_clk: dma0_clk@30 {
1238 #clock-cells = <0>;
1239 reg = <30>;
1240 };
1241
1242 dma1_clk: dma1_clk@31 {
1243 #clock-cells = <0>;
1244 reg = <31>;
1245 };
1246
1247 uhphs_clk: uhphs_clk@32 {
1248 #clock-cells = <0>;
1249 reg = <32>;
1250 };
1251
1252 udphs_clk: udphs_clk@33 {
1253 #clock-cells = <0>;
1254 reg = <33>;
1255 };
1256
1257 isi_clk: isi_clk@37 {
1258 #clock-cells = <0>;
1259 reg = <37>;
1260 };
1261
1262 ssc0_clk: ssc0_clk@38 {
1263 #clock-cells = <0>;
1264 reg = <38>;
1265 atmel,clk-output-range = <0 66000000>;
1266 };
1267
1268 ssc1_clk: ssc1_clk@39 {
1269 #clock-cells = <0>;
1270 reg = <39>;
1271 atmel,clk-output-range = <0 66000000>;
1272 };
1273
1274 sha_clk: sha_clk@42 {
1275 #clock-cells = <0>;
1276 reg = <42>;
1277 };
1278
1279 aes_clk: aes_clk@43 {
1280 #clock-cells = <0>;
1281 reg = <43>;
1282 };
1283
1284 tdes_clk: tdes_clk@44 {
1285 #clock-cells = <0>;
1286 reg = <44>;
1287 };
1288
1289 trng_clk: trng_clk@45 {
1290 #clock-cells = <0>;
1291 reg = <45>;
1292 };
1293
1294 fuse_clk: fuse_clk@48 {
1295 #clock-cells = <0>;
1296 reg = <48>;
1297 };
1298
1299 mpddr_clk: mpddr_clk@49 {
1300 #clock-cells = <0>;
1301 reg = <49>;
1302 };
1303 };
1304 };
1305
1306 rstc@fffffe00 {
1307 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1308 reg = <0xfffffe00 0x10>;
1309 clocks = <&clk32k>;
1310 };
1311
1312 shutdown-controller@fffffe10 {
1313 compatible = "atmel,at91sam9x5-shdwc";
1314 reg = <0xfffffe10 0x10>;
1315 clocks = <&clk32k>;
1316 };
1317
1318 pit: timer@fffffe30 {
1319 compatible = "atmel,at91sam9260-pit";
1320 reg = <0xfffffe30 0xf>;
1321 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1322 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]1323 bootph-all;
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1324 };
1325
1326 watchdog@fffffe40 {
1327 compatible = "atmel,at91sam9260-wdt";
1328 reg = <0xfffffe40 0x10>;
1329 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1330 clocks = <&clk32k>;
1331 atmel,watchdog-type = "hardware";
1332 atmel,reset-type = "all";
1333 atmel,dbg-halt;
1334 status = "disabled";
1335 };
1336
1337 sckc@fffffe50 {
1338 compatible = "atmel,at91sam9x5-sckc";
1339 reg = <0xfffffe50 0x4>;
1340
1341 slow_rc_osc: slow_rc_osc {
1342 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1343 #clock-cells = <0>;
1344 clock-frequency = <32768>;
1345 clock-accuracy = <50000000>;
1346 atmel,startup-time-usec = <75>;
1347 };
1348
1349 slow_osc: slow_osc {
1350 compatible = "atmel,at91sam9x5-clk-slow-osc";
1351 #clock-cells = <0>;
1352 clocks = <&slow_xtal>;
1353 atmel,startup-time-usec = <1200000>;
1354 };
1355
1356 clk32k: slowck {
1357 compatible = "atmel,at91sam9x5-clk-slow";
1358 #clock-cells = <0>;
1359 clocks = <&slow_rc_osc &slow_osc>;
1360 };
1361 };
1362
1363 rtc@fffffeb0 {
1364 compatible = "atmel,at91rm9200-rtc";
1365 reg = <0xfffffeb0 0x30>;
1366 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1367 clocks = <&clk32k>;
1368 };
1369 };
1370
1371 usb0: gadget@00500000 {
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1374 compatible = "atmel,sama5d3-udc";
1375 reg = <0x00500000 0x100000
1376 0xf8030000 0x4000>;
1377 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1378 clocks = <&udphs_clk>, <&utmi>;
1379 clock-names = "pclk", "hclk";
1380 status = "disabled";
1381
1382 ep0: endpoint@0 {
1383 reg = <0>;
1384 atmel,fifo-size = <64>;
1385 atmel,nb-banks = <1>;
1386 };
1387
1388 ep1: endpoint@1 {
1389 reg = <1>;
1390 atmel,fifo-size = <1024>;
1391 atmel,nb-banks = <3>;
1392 atmel,can-dma;
1393 atmel,can-isoc;
1394 };
1395
1396 ep2: endpoint@2 {
1397 reg = <2>;
1398 atmel,fifo-size = <1024>;
1399 atmel,nb-banks = <3>;
1400 atmel,can-dma;
1401 atmel,can-isoc;
1402 };
1403
1404 ep3: endpoint@3 {
1405 reg = <3>;
1406 atmel,fifo-size = <1024>;
1407 atmel,nb-banks = <2>;
1408 atmel,can-dma;
1409 };
1410
1411 ep4: endpoint@4 {
1412 reg = <4>;
1413 atmel,fifo-size = <1024>;
1414 atmel,nb-banks = <2>;
1415 atmel,can-dma;
1416 };
1417
1418 ep5: endpoint@5 {
1419 reg = <5>;
1420 atmel,fifo-size = <1024>;
1421 atmel,nb-banks = <2>;
1422 atmel,can-dma;
1423 };
1424
1425 ep6: endpoint@6 {
1426 reg = <6>;
1427 atmel,fifo-size = <1024>;
1428 atmel,nb-banks = <2>;
1429 atmel,can-dma;
1430 };
1431
1432 ep7i: endpoint@7 {
1433 reg = <7>;
1434 atmel,fifo-size = <1024>;
1435 atmel,nb-banks = <2>;
1436 atmel,can-dma;
1437 };
1438
1439 ep8: endpoint@8 {
1440 reg = <8>;
1441 atmel,fifo-size = <1024>;
1442 atmel,nb-banks = <2>;
1443 };
1444
1445 ep9: endpoint@9 {
1446 reg = <9>;
1447 atmel,fifo-size = <1024>;
1448 atmel,nb-banks = <2>;
1449 };
1450
Eugen Hristev6d9f7b82020-06-05 09:51:31 +0300[diff] [blame]1451 ep10: endpoint@a {
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1452 reg = <10>;
1453 atmel,fifo-size = <1024>;
1454 atmel,nb-banks = <2>;
1455 };
1456
Eugen Hristev6d9f7b82020-06-05 09:51:31 +0300[diff] [blame]1457 ep11: endpoint@b {
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1458 reg = <11>;
1459 atmel,fifo-size = <1024>;
1460 atmel,nb-banks = <2>;
1461 };
1462
Eugen Hristev6d9f7b82020-06-05 09:51:31 +0300[diff] [blame]1463 ep12: endpoint@c {
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1464 reg = <12>;
1465 atmel,fifo-size = <1024>;
1466 atmel,nb-banks = <2>;
1467 };
1468
Eugen Hristev6d9f7b82020-06-05 09:51:31 +0300[diff] [blame]1469 ep13: endpoint@d {
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1470 reg = <13>;
1471 atmel,fifo-size = <1024>;
1472 atmel,nb-banks = <2>;
1473 };
1474
Eugen Hristev6d9f7b82020-06-05 09:51:31 +0300[diff] [blame]1475 ep14: endpoint@e {
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1476 reg = <14>;
1477 atmel,fifo-size = <1024>;
1478 atmel,nb-banks = <2>;
1479 };
1480
Eugen Hristev6d9f7b82020-06-05 09:51:31 +0300[diff] [blame]1481 ep15: endpoint@f {
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1482 reg = <15>;
1483 atmel,fifo-size = <1024>;
1484 atmel,nb-banks = <2>;
1485 };
1486 };
1487
1488 usb1: ohci@00600000 {
1489 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1490 reg = <0x00600000 0x100000>;
1491 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1492 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1493 clock-names = "ohci_clk", "hclk", "uhpck";
1494 status = "disabled";
1495 };
1496
1497 usb2: ehci@00700000 {
1498 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1499 reg = <0x00700000 0x100000>;
1500 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1501 clocks = <&utmi>, <&uhphs_clk>;
1502 clock-names = "usb_clk", "ehci_clk";
1503 status = "disabled";
1504 };
1505
1506 nand0: nand@60000000 {
1507 compatible = "atmel,at91rm9200-nand";
1508 #address-cells = <1>;
1509 #size-cells = <1>;
1510 ranges;
1511 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1512 0xffffc070 0x00000490 /* SMC PMECC regs */
1513 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1514 0x00110000 0x00018000 /* ROM code */
1515 >;
1516 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1517 atmel,nand-addr-offset = <21>;
1518 atmel,nand-cmd-offset = <22>;
1519 atmel,nand-has-dma;
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1522 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1523 status = "disabled";
1524
1525 nfc@70000000 {
1526 compatible = "atmel,sama5d3-nfc";
1527 #address-cells = <1>;
1528 #size-cells = <1>;
1529 reg = <
1530 0x70000000 0x08000000 /* NFC Command Registers */
1531 0xffffc000 0x00000070 /* NFC HSMC regs */
1532 0x00200000 0x00100000 /* NFC SRAM banks */
1533 >;
1534 clocks = <&hsmc_clk>;
1535 };
1536 };
1537 };
Eugen Hristev5bdd47d2018-09-18 10:35:54 +0300[diff] [blame]1538
1539 onewire_tm: onewire {
1540 compatible = "w1-gpio";
1541 status = "disabled";
1542 };
Wenyou Yang35736f52017-03-24 09:18:41 +0800[diff] [blame]1543};