blob: 74e8bfc43147615d5139510833894794e4880846 [file] [log] [blame]
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06007#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010010#include <asm/io.h>
11#include <asm/addrspace.h>
12#include <asm/types.h>
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010013#include <spi.h>
Lars Povlsenc89dc232019-01-02 09:52:26 +010014#include <led.h>
Gregory CLEMENT550ee062019-01-17 17:07:14 +010015#include <wait_bit.h>
Horatiu Vultur41935df2019-04-24 11:27:58 +020016#include <miiphy.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010018
19DECLARE_GLOBAL_DATA_PTR;
20
Lars Povlsen90392822018-12-20 09:56:05 +010021enum {
22 BOARD_TYPE_PCB120 = 0xAABBCC00,
23 BOARD_TYPE_PCB123,
24};
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010025
Gregory CLEMENT550ee062019-01-17 17:07:14 +010026void mscc_switch_reset(bool enter)
27{
28 /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
29 mscc_gpio_set_alternate(19, 2);
30
31 debug("applying SwC reset\n");
32
33 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
34 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
35
36 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
37 PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
38 pr_err("Tiemout while waiting for switch reset\n");
39
40 /*
41 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
42 * not reset) (Order is important)
43 */
44 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
45 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
46 mscc_gpio_set_alternate(19, 0);
47}
48
Horatiu Vultur41935df2019-04-24 11:27:58 +020049int board_phy_config(struct phy_device *phydev)
50{
51 if (gd->board_type == BOARD_TYPE_PCB123)
52 return 0;
53
54 phy_write(phydev, 0, 31, 0x10);
55 phy_write(phydev, 0, 18, 0x80F0);
56 while (phy_read(phydev, 0, 18) & 0x8000)
57 ;
58 phy_write(phydev, 0, 31, 0);
59
60 return 0;
61}
62
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010063void board_debug_uart_init(void)
64{
65 /* too early for the pinctrl driver, so configure the UART pins here */
Lars Povlsen90392822018-12-20 09:56:05 +010066 mscc_gpio_set_alternate(6, 1);
67 mscc_gpio_set_alternate(7, 1);
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010068}
69
70int board_early_init_r(void)
71{
72 /* Prepare SPI controller to be used in master mode */
73 writel(0, BASE_CFG + ICPU_SW_MODE);
74 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
75 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
76 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
77
78 /* Address of boot parameters */
79 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
Lars Povlsenc89dc232019-01-02 09:52:26 +010080
81 /* LED setup */
82 if (IS_ENABLED(CONFIG_LED))
83 led_default_state();
84
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010085 return 0;
86}
Lars Povlsen90392822018-12-20 09:56:05 +010087
88static void do_board_detect(void)
89{
90 u16 dummy = 0;
91
92 /* Enable MIIM */
93 mscc_gpio_set_alternate(14, 1);
94 mscc_gpio_set_alternate(15, 1);
95 if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
96 gd->board_type = BOARD_TYPE_PCB120;
97 else
98 gd->board_type = BOARD_TYPE_PCB123;
99}
100
101#if defined(CONFIG_MULTI_DTB_FIT)
102int board_fit_config_name_match(const char *name)
103{
104 if (gd->board_type == BOARD_TYPE_PCB120 &&
105 strcmp(name, "ocelot_pcb120") == 0)
106 return 0;
107
108 if (gd->board_type == BOARD_TYPE_PCB123 &&
109 strcmp(name, "ocelot_pcb123") == 0)
110 return 0;
111
112 return -1;
113}
114#endif
115
116#if defined(CONFIG_DTB_RESELECT)
117int embedded_dtb_select(void)
118{
119 do_board_detect();
120 fdtdec_setup();
121
122 return 0;
123}
124#endif