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git01.mediatek.com / filogic / uboot / d20e4154553906858d498e3c564dbc687cd5e448 / . / drivers / spi / cadence_qspi.h
blob: 055900def001ffe2e6a1d76cfdbb5534b31fc5c3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]2/*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]5 */
6
7#ifndef __CADENCE_QSPI_H__
8#define __CADENCE_QSPI_H__
9
10#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
11
12#define CQSPI_NO_DECODER_MAX_CS 4
13#define CQSPI_DECODER_MAX_CS 16
14#define CQSPI_READ_CAPTURE_MAX_DELAY 16
15
16struct cadence_spi_platdata {
17 unsigned int max_hz;
18 void *regbase;
19 void *ahbbase;
Jason Rush1b4df5e2018-01-23 17:13:09 -0600[diff] [blame]20 bool is_decoded_cs;
21 u32 fifo_depth;
22 u32 fifo_width;
23 u32 trigger_address;
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]24
Jason Rush1b4df5e2018-01-23 17:13:09 -0600[diff] [blame]25 /* Flash parameters */
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]26 u32 page_size;
27 u32 block_size;
28 u32 tshsl_ns;
29 u32 tsd2d_ns;
30 u32 tchsh_ns;
31 u32 tslch_ns;
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]32};
33
34struct cadence_spi_priv {
35 void *regbase;
36 void *ahbbase;
37 size_t cmd_len;
38 u8 cmd_buf[32];
39 size_t data_len;
40
41 int qspi_is_init;
42 unsigned int qspi_calibrated_hz;
43 unsigned int qspi_calibrated_cs;
Chin Liang See36431f92015-10-17 08:31:55 -0500[diff] [blame]44 unsigned int previous_hz;
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]45};
46
47/* Functions call declaration */
48void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
49void cadence_qspi_apb_controller_enable(void *reg_base_addr);
50void cadence_qspi_apb_controller_disable(void *reg_base_addr);
51
52int cadence_qspi_apb_command_read(void *reg_base_addr,
53 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
54int cadence_qspi_apb_command_write(void *reg_base_addr,
55 unsigned int cmdlen, const u8 *cmdbuf,
56 unsigned int txlen, const u8 *txbuf);
57
58int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
Vignesh R4ca60192016-07-06 10:20:56 +0530[diff] [blame]59 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]60int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
61 unsigned int rxlen, u8 *rxbuf);
62int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
63 unsigned int cmdlen, const u8 *cmdbuf);
64int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
65 unsigned int txlen, const u8 *txbuf);
66
67void cadence_qspi_apb_chipselect(void *reg_base,
68 unsigned int chip_select, unsigned int decoder_enable);
Phil Edworthyeef2edc2016-11-29 12:58:31 +0000[diff] [blame]69void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]70void cadence_qspi_apb_config_baudrate_div(void *reg_base,
71 unsigned int ref_clk_hz, unsigned int sclk_hz);
72void cadence_qspi_apb_delay(void *reg_base,
73 unsigned int ref_clk, unsigned int sclk_hz,
74 unsigned int tshsl_ns, unsigned int tsd2d_ns,
75 unsigned int tchsh_ns, unsigned int tslch_ns);
76void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
77void cadence_qspi_apb_readdata_capture(void *reg_base,
78 unsigned int bypass, unsigned int delay);
79
80#endif /* __CADENCE_QSPI_H__ */