| Marek Vasut | b700f03 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * include/configs/condor.h |
| 4 | * This file is Condor board configuration. |
| 5 | * |
| 6 | * Copyright (C) 2019 Renesas Electronics Corporation |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONDOR_H |
| 10 | #define __CONDOR_H |
| 11 | |
| 12 | #include "rcar-gen3-common.h" |
| 13 | |
| Marek Vasut | b700f03 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 14 | /* Environment compatibility */ |
| Marek Vasut | b700f03 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 15 | |
| 16 | /* SH Ether */ |
| Tom Rini | 9996ab8 | 2022-12-04 10:13:52 -0500 | [diff] [blame] | 17 | #define CFG_SH_ETHER_USE_PORT 0 |
| Tom Rini | 45ec5fd | 2022-12-04 10:13:50 -0500 | [diff] [blame] | 18 | #define CFG_SH_ETHER_PHY_ADDR 0x1 |
| Tom Rini | b210dc1 | 2022-12-04 10:13:51 -0500 | [diff] [blame] | 19 | #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII |
| Tom Rini | 872054f | 2022-12-04 10:13:49 -0500 | [diff] [blame] | 20 | #define CFG_SH_ETHER_CACHE_WRITEBACK |
| Tom Rini | a44cb16 | 2022-12-04 10:13:48 -0500 | [diff] [blame] | 21 | #define CFG_SH_ETHER_CACHE_INVALIDATE |
| Tom Rini | dd2eba0 | 2022-12-04 10:13:47 -0500 | [diff] [blame] | 22 | #define CFG_SH_ETHER_ALIGNE_SIZE 64 |
| Marek Vasut | b700f03 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 23 | |
| 24 | /* Board Clock */ |
| 25 | /* XTAL_CLK : 33.33MHz */ |
| Marek Vasut | b700f03 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 26 | |
| Marek Vasut | b700f03 | 2019-07-29 19:59:44 +0200 | [diff] [blame] | 27 | #endif /* __CONDOR_H */ |