| Tianling Shen | 0c8dea5 | 2023-05-20 19:20:50 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd |
| 4 | * (C) Copyright 2020 David Bauer |
| 5 | */ |
| 6 | |
| 7 | #include "rk3328-u-boot.dtsi" |
| 8 | #include "rk3328-sdram-lpddr3-666.dtsi" |
| 9 | / { |
| 10 | chosen { |
| 11 | u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; |
| 12 | }; |
| 13 | }; |
| 14 | |
| 15 | &gpio0 { |
| 16 | bootph-pre-ram; |
| 17 | }; |
| 18 | |
| 19 | &pinctrl { |
| 20 | bootph-pre-ram; |
| 21 | }; |
| 22 | |
| 23 | &sdmmc0m1_pin { |
| 24 | bootph-pre-ram; |
| 25 | }; |
| 26 | |
| 27 | &pcfg_pull_up_4ma { |
| 28 | bootph-pre-ram; |
| 29 | }; |
| 30 | |
| 31 | /* Need this and all the pinctrl/gpio stuff above to set pinmux */ |
| 32 | &vcc_sd { |
| 33 | bootph-pre-ram; |
| 34 | }; |
| 35 | |
| 36 | &gmac2io { |
| 37 | snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; |
| 38 | snps,reset-active-low; |
| 39 | snps,reset-delays-us = <0 10000 50000>; |
| 40 | }; |
| 41 | |
| 42 | &spi0 { |
| 43 | spi_flash: spiflash@0 { |
| 44 | bootph-all; |
| 45 | }; |
| 46 | }; |