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git01.mediatek.com / filogic / uboot / d16f3d7b40e1e4c099b5c4e46959242022abb446 / . / arch / arm / dts / k3-j721e-r5-sk.dts
blob: b0c108e9693114ce70f800bccc7eb75d44a80e6e [file] [log] [blame]
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]8#include "k3-j721e-sk.dts"
Sinthu Rajabb23e8e2021-11-02 19:59:45 +0530[diff] [blame]9#include "k3-j721e-ddr-sk-lp4-4266.dtsi"
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]10#include "k3-j721e-ddr.dtsi"
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]11#include "k3-j721e-sk-u-boot.dtsi"
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]12
13/ {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]14 chosen {
15 tick-timer = &mcu_timer0;
16 };
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]17
18 aliases {
19 remoteproc0 = &sysctrler;
20 remoteproc1 = &a72_0;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]21 };
22
23 a72_0: a72@0 {
24 compatible = "ti,am654-rproc";
25 reg = <0x0 0x00a90000 0x0 0x10>;
26 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry9a160582023-04-14 09:47:53 +0530[diff] [blame]27 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
28 <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]29 resets = <&k3_reset 202 0>;
30 clocks = <&k3_clks 61 1>;
31 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
32 assigned-clock-rates = <2000000000>, <200000000>;
33 ti,sci = <&dmsc>;
34 ti,sci-proc-id = <32>;
35 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]37 };
38
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]39 dm_tifs: dm-tifs {
40 compatible = "ti,j721e-dm-sci";
41 ti,host-id = <3>;
42 ti,secure-host;
43 mbox-names = "rx", "tx";
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]44 mboxes= <&secure_proxy_mcu 21>,
45 <&secure_proxy_mcu 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]47 };
48};
49
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]50&mcu_timer0 {
51 status = "okay";
52 bootph-pre-ram;
53};
54
55&secure_proxy_mcu {
56 bootph-pre-ram;
57 status = "okay";
58};
59
60&cbass_mcu_wakeup {
61 sysctrler: sysctrler {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]63 compatible = "ti,am654-system-controller";
64 mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
65 mbox-names = "tx", "rx";
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]66 };
67};
68
69&dmsc {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]70 mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]71 mbox-names = "tx", "rx", "notify";
72 ti,host-id = <4>;
73 ti,secure-host;
74};
75
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]76&mcu_ringacc {
77 ti,sci = <&dm_tifs>;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]78};
79
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]80&mcu_udmap {
81 ti,sci = <&dm_tifs>;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]82};
83
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]84&wkup_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]86};
87
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]88&mcu_uart0_pins_default {
89 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]90};
91
92&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]94 tps659412: tps659412@48 {
95 reg = <0x48>;
96 compatible = "ti,tps659412";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]98 pinctrl-names = "default";
99 pinctrl-0 = <&wkup_i2c0_pins_default>;
100 clock-frequency = <400000>;
101
102 regulators: regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]104 /* 3 Phase Buck */
105 buck123_reg: buck123 {
106 /* VDD_CPU */
107 regulator-name = "buck123";
108 regulator-min-microvolt = <800000>;
109 regulator-max-microvolt = <1250000>;
110 regulator-always-on;
111 regulator-boot-on;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]113 };
114 };
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]115
116 esm: esm {
117 compatible = "ti,tps659413-esm";
118 bootph-pre-ram;
119 };
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]120 };
121};
122
123&wkup_vtm0 {
124 vdd-supply-2 = <&buck123_reg>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]126};
127
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]128&ospi0 {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]129 /* Address change for data region (32-bit) */
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]130 reg = <0x0 0x47040000 0x0 0x100>,
131 <0x0 0x50000000 0x0 0x8000000>;
Sinthu Raja2c8da5d2022-02-09 15:06:56 +0530[diff] [blame]132};