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git01.mediatek.com / filogic / uboot / d16f3d7b40e1e4c099b5c4e46959242022abb446 / . / arch / arm / dts / imxrt1020-evk.dts
blob: d4d1de4ea840125e7e3706a21f8e78cc0fc3ece7 [file] [log] [blame]
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2020
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7/dts-v1/;
8#include "imxrt1020.dtsi"
Jesse Taube62394a72022-03-17 14:33:20 -0400[diff] [blame]9#include "imxrt1020-pinfunc.h"
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]10
11/ {
12 model = "NXP IMXRT1020-evk board";
13 compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
14
15 chosen {
16 bootargs = "root=/dev/ram";
17 stdout-path = "serial0:115200n8";
Giulio Benetti0fe94c02021-05-13 12:18:35 +0200[diff] [blame]18 tick-timer = &gpt1;
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]19 };
20
21 memory {
Giulio Benetticd90a192021-05-13 12:18:37 +0200[diff] [blame]22 device_type = "memory";
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]23 reg = <0x80000000 0x2000000>;
24 };
25};
26
27&lpuart1 { /* console */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_lpuart1>;
30 status = "okay";
31};
32
33&semc {
34 /*
35 * Memory configuration from sdram datasheet IS42S16160J-6TLI
36 */
37 fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
38 MUX_CSX0_SDRAM_CS1
39 0
40 0
41 0
42 0>;
43 fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
44 BL_8
45 COL_9BITS
46 CL_3>;
47 fsl,sdram-timing = /bits/ 8 <0x2
48 0x2
49 0x9
50 0x1
51 0x5
52 0x6
53
54 0x20
55 0x09
56 0x01
57 0x00
58
59 0x04
60 0x0A
61 0x21
62 0x50>;
63
64 bank1: bank@0 {
65 fsl,base-address = <0x80000000>;
66 fsl,memory-size = <MEM_SIZE_32M>;
67 };
68};
69
70&iomuxc {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_lpuart1>;
73
74 imxrt1020-evk {
75 pinctrl_lpuart1: lpuart1grp {
76 fsl,pins = <
77 MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
78 0xf1
79 MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
80 0xf1
81 >;
82 };
83
84 pinctrl_semc: semcgrp {
85 fsl,pins = <
86 MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
87 0xf1 /* SEMC_D0 */
88 MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
89 0xf1 /* SEMC_D1 */
90 MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
91 0xf1 /* SEMC_D2 */
92 MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
93 0xf1 /* SEMC_D3 */
94 MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
95 0xf1 /* SEMC_D4 */
96 MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
97 0xf1 /* SEMC_D5 */
98 MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
99 0xf1 /* SEMC_D6 */
100 MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
101 0xf1 /* SEMC_D7 */
102 MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
103 0xf1 /* SEMC_DM0 */
104 MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
105 0xf1 /* SEMC_A0 */
106 MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
107 0xf1 /* SEMC_CAS */
108 MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
109 0xf1 /* SEMC_RAS */
110 MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
111 0xf1 /* SEMC_CS0 */
112 MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
113 0xf1 /* SEMC_BA0 */
114 MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
115 0xf1 /* SEMC_BA1 */
116 MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
117 0xf1 /* SEMC_A10 */
118 MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
119 0xf1 /* SEMC_A0 */
120 MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
121 0xf1 /* SEMC_A1 */
122 MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
123 0xf1 /* SEMC_A2 */
124 MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
125 0xf1 /* SEMC_A3 */
126 MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
127 0xf1 /* SEMC_A4 */
128 MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
129 0xf1 /* SEMC_A5 */
130 MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
131 0xf1 /* SEMC_A6 */
132 MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
133 0xf1 /* SEMC_A7 */
134 MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
135 0xf1 /* SEMC_A8 */
136 MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
137 0xf1 /* SEMC_A9 */
138 MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
139 0xf1 /* SEMC_A11 */
140 MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
141 0xf1 /* SEMC_A12 */
142 MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
143 (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
144 MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
145 0xf1 /* SEMC_CKE */
146 MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
147 0xf1 /* SEMC_CLK */
148 MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
149 0xf1 /* SEMC_DM01 */
150 MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
151 0xf1 /* SEMC_D8 */
152 MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
153 0xf1 /* SEMC_D9 */
154 MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
155 0xf1 /* SEMC_D10 */
156 MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
157 0xf1 /* SEMC_D11 */
158 MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
159 0xf1 /* SEMC_D12 */
160 MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
161 0xf1 /* SEMC_D13 */
162 MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
163 0xf1 /* SEMC_D14 */
164 MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
165 0xf1 /* SEMC_D15 */
166 >;
167 };
168
169 pinctrl_usdhc0: usdhc0grp {
170 fsl,pins = <
171 MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
172 0x1B000
173 MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
174 0x17061
175 MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
176 0x17061
177 MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
178 0x17061
179 MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
180 0x17061
181 MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
182 0x17061
183 MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
184 0x17061
185 >;
186 };
187 };
188};
189
Giulio Benetti857330e2021-05-13 12:18:34 +0200[diff] [blame]190&gpt1 {
191 status = "okay";
192};
193
Giulio Benettid1203ca2020-02-18 20:02:55 +0100[diff] [blame]194&usdhc1 {
195 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
196 pinctrl-0 = <&pinctrl_usdhc0>;
197 pinctrl-1 = <&pinctrl_usdhc0>;
198 pinctrl-2 = <&pinctrl_usdhc0>;
199 pinctrl-3 = <&pinctrl_usdhc0>;
200 status = "okay";
201
202 cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
203};