| Andrew Davis | ebc98d9 | 2023-04-11 13:24:54 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| Adam Ford | b0c1ff2 | 2017-09-19 20:32:10 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Device Tree Source for OMAP3 clock data |
| 4 | * |
| 5 | * Copyright (C) 2013 Texas Instruments, Inc. |
| Adam Ford | b0c1ff2 | 2017-09-19 20:32:10 -0500 | [diff] [blame] | 6 | */ |
| 7 | &scm_clocks { |
| 8 | emac_ick: emac_ick@32c { |
| 9 | #clock-cells = <0>; |
| 10 | compatible = "ti,am35xx-gate-clock"; |
| 11 | clocks = <&ipss_ick>; |
| 12 | reg = <0x032c>; |
| 13 | ti,bit-shift = <1>; |
| 14 | }; |
| 15 | |
| 16 | emac_fck: emac_fck@32c { |
| 17 | #clock-cells = <0>; |
| 18 | compatible = "ti,gate-clock"; |
| 19 | clocks = <&rmii_ck>; |
| 20 | reg = <0x032c>; |
| 21 | ti,bit-shift = <9>; |
| 22 | }; |
| 23 | |
| 24 | vpfe_ick: vpfe_ick@32c { |
| 25 | #clock-cells = <0>; |
| 26 | compatible = "ti,am35xx-gate-clock"; |
| 27 | clocks = <&ipss_ick>; |
| 28 | reg = <0x032c>; |
| 29 | ti,bit-shift = <2>; |
| 30 | }; |
| 31 | |
| 32 | vpfe_fck: vpfe_fck@32c { |
| 33 | #clock-cells = <0>; |
| 34 | compatible = "ti,gate-clock"; |
| 35 | clocks = <&pclk_ck>; |
| 36 | reg = <0x032c>; |
| 37 | ti,bit-shift = <10>; |
| 38 | }; |
| 39 | |
| 40 | hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { |
| 41 | #clock-cells = <0>; |
| 42 | compatible = "ti,am35xx-gate-clock"; |
| 43 | clocks = <&ipss_ick>; |
| 44 | reg = <0x032c>; |
| 45 | ti,bit-shift = <0>; |
| 46 | }; |
| 47 | |
| 48 | hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { |
| 49 | #clock-cells = <0>; |
| 50 | compatible = "ti,gate-clock"; |
| 51 | clocks = <&sys_ck>; |
| 52 | reg = <0x032c>; |
| 53 | ti,bit-shift = <8>; |
| 54 | }; |
| 55 | |
| 56 | hecc_ck: hecc_ck@32c { |
| 57 | #clock-cells = <0>; |
| 58 | compatible = "ti,am35xx-gate-clock"; |
| 59 | clocks = <&sys_ck>; |
| 60 | reg = <0x032c>; |
| 61 | ti,bit-shift = <3>; |
| 62 | }; |
| 63 | }; |
| 64 | &cm_clocks { |
| 65 | ipss_ick: ipss_ick@a10 { |
| 66 | #clock-cells = <0>; |
| 67 | compatible = "ti,am35xx-interface-clock"; |
| 68 | clocks = <&core_l3_ick>; |
| 69 | reg = <0x0a10>; |
| 70 | ti,bit-shift = <4>; |
| 71 | }; |
| 72 | |
| 73 | rmii_ck: rmii_ck { |
| 74 | #clock-cells = <0>; |
| 75 | compatible = "fixed-clock"; |
| 76 | clock-frequency = <50000000>; |
| 77 | }; |
| 78 | |
| 79 | pclk_ck: pclk_ck { |
| 80 | #clock-cells = <0>; |
| 81 | compatible = "fixed-clock"; |
| 82 | clock-frequency = <27000000>; |
| 83 | }; |
| 84 | |
| 85 | uart4_ick_am35xx: uart4_ick_am35xx@a10 { |
| 86 | #clock-cells = <0>; |
| 87 | compatible = "ti,omap3-interface-clock"; |
| 88 | clocks = <&core_l4_ick>; |
| 89 | reg = <0x0a10>; |
| 90 | ti,bit-shift = <23>; |
| 91 | }; |
| 92 | |
| 93 | uart4_fck_am35xx: uart4_fck_am35xx@a00 { |
| 94 | #clock-cells = <0>; |
| 95 | compatible = "ti,wait-gate-clock"; |
| 96 | clocks = <&core_48m_fck>; |
| 97 | reg = <0x0a00>; |
| 98 | ti,bit-shift = <23>; |
| 99 | }; |
| 100 | }; |
| 101 | |
| 102 | &cm_clockdomains { |
| 103 | core_l3_clkdm: core_l3_clkdm { |
| 104 | compatible = "ti,clockdomain"; |
| 105 | clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, |
| 106 | <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, |
| 107 | <&hecc_ck>; |
| 108 | }; |
| 109 | |
| 110 | core_l4_clkdm: core_l4_clkdm { |
| 111 | compatible = "ti,clockdomain"; |
| 112 | clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, |
| 113 | <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, |
| 114 | <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, |
| 115 | <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, |
| 116 | <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, |
| 117 | <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, |
| 118 | <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, |
| 119 | <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, |
| 120 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, |
| 121 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, |
| 122 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, |
| 123 | <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; |
| 124 | }; |
| 125 | }; |