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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babiccacdd2b2010-04-18 19:27:44 +02002/*
3 * (C) Copyright 2010
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
Stefano Babiccacdd2b2010-04-18 19:27:44 +02007 */
8
Stefano Babiccacdd2b2010-04-18 19:27:44 +02009#ifndef __MC13892_H__
10#define __MC13892_H__
11
12/* REG_CHARGE */
13
Shawn Guo4546eb72010-10-27 23:36:04 +080014#define VCHRG0 (1 << 0)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020015#define VCHRG1 (1 << 1)
16#define VCHRG2 (1 << 2)
17#define ICHRG0 (1 << 3)
18#define ICHRG1 (1 << 4)
19#define ICHRG2 (1 << 5)
20#define ICHRG3 (1 << 6)
Shawn Guo4546eb72010-10-27 23:36:04 +080021#define TREN (1 << 7)
22#define ACKLPB (1 << 8)
23#define THCHKB (1 << 9)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020024#define FETOVRD (1 << 10)
25#define FETCTRL (1 << 11)
26#define RVRSMODE (1 << 13)
Shawn Guo4546eb72010-10-27 23:36:04 +080027#define PLIM0 (1 << 15)
28#define PLIM1 (1 << 16)
29#define PLIMDIS (1 << 17)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020030#define CHRGLEDEN (1 << 18)
Shawn Guo4546eb72010-10-27 23:36:04 +080031#define CHGTMRRST (1 << 19)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020032#define CHGRESTART (1 << 20)
33#define CHGAUTOB (1 << 21)
34#define CYCLB (1 << 22)
35#define CHGAUTOVIB (1 << 23)
36
37/* REG_SETTING_0/1 */
38#define VO_1_20V 0
39#define VO_1_30V 1
40#define VO_1_50V 2
41#define VO_1_80V 3
42#define VO_1_10V 4
43#define VO_2_00V 5
44#define VO_2_77V 6
45#define VO_2_40V 7
46
47#define VIOL 2
48#define VDIG 4
49#define VGEN 6
50
51/* SWxMode for Normal/Standby Mode */
52#define SWMODE_OFF_OFF 0
53#define SWMODE_PWM_OFF 1
54#define SWMODE_PWMPS_OFF 2
55#define SWMODE_PFM_OFF 3
56#define SWMODE_AUTO_OFF 4
57#define SWMODE_PWM_PWM 5
58#define SWMODE_PWM_AUTO 6
59#define SWMODE_AUTO_AUTO 8
60#define SWMODE_PWM_PWMPS 9
61#define SWMODE_PWMS_PWMPS 10
62#define SWMODE_PWMS_AUTO 11
63#define SWMODE_AUTO_PFM 12
64#define SWMODE_PWM_PFM 13
65#define SWMODE_PWMS_PFM 14
66#define SWMODE_PFM_PFM 15
67#define SWMODE_MASK 0x0F
68
69#define SWMODE1_SHIFT 0
70#define SWMODE2_SHIFT 10
71#define SWMODE3_SHIFT 0
72#define SWMODE4_SHIFT 8
73
74/* Fields in REG_SETTING_1 */
75#define VVIDEO_2_7 (0 << 2)
76#define VVIDEO_2_775 (1 << 2)
77#define VVIDEO_2_5 (2 << 2)
78#define VVIDEO_2_6 (3 << 2)
79#define VVIDEO_MASK (3 << 2)
80#define VAUDIO_2_3 (0 << 4)
81#define VAUDIO_2_5 (1 << 4)
82#define VAUDIO_2_775 (2 << 4)
83#define VAUDIO_3_0 (3 << 4)
84#define VAUDIO_MASK (3 << 4)
85#define VSD_1_8 (0 << 6)
86#define VSD_2_0 (1 << 6)
87#define VSD_2_6 (2 << 6)
88#define VSD_2_7 (3 << 6)
89#define VSD_2_8 (4 << 6)
90#define VSD_2_9 (5 << 6)
91#define VSD_3_0 (6 << 6)
92#define VSD_3_15 (7 << 6)
93#define VSD_MASK (7 << 6)
94#define VGEN1_1_2 0
95#define VGEN1_1_5 1
96#define VGEN1_2_775 2
97#define VGEN1_3_15 3
98#define VGEN1_MASK 3
99#define VGEN2_1_2 (0 << 6)
100#define VGEN2_1_5 (1 << 6)
101#define VGEN2_1_6 (2 << 6)
102#define VGEN2_1_8 (3 << 6)
103#define VGEN2_2_7 (4 << 6)
104#define VGEN2_2_8 (5 << 6)
105#define VGEN2_3_0 (6 << 6)
106#define VGEN2_3_15 (7 << 6)
107#define VGEN2_MASK (7 << 6)
108
109/* Fields in REG_SETTING_1 */
110#define VGEN3_1_8 (0 << 14)
111#define VGEN3_2_9 (1 << 14)
112#define VGEN3_MASK (1 << 14)
113#define VDIG_1_05 (0 << 4)
114#define VDIG_1_25 (1 << 4)
115#define VDIG_1_65 (2 << 4)
116#define VDIG_1_8 (3 << 4)
117#define VDIG_MASK (3 << 4)
118#define VCAM_2_5 (0 << 16)
119#define VCAM_2_6 (1 << 16)
120#define VCAM_2_75 (2 << 16)
121#define VCAM_3_0 (3 << 16)
122#define VCAM_MASK (3 << 16)
123
Marek Vasut030808f2011-09-28 02:07:26 +0000124/* Reg Mode 0 */
125#define VGEN1EN (1 << 0)
126#define VGEN1STBY (1 << 1)
127#define VGEN1MODE (1 << 2)
128#define VIOHIEN (1 << 3)
129#define VIOHISTBY (1 << 4)
130#define VDIGEN (1 << 9)
131#define VDIGSTBY (1 << 10)
132#define VGEN2EN (1 << 12)
133#define VGEN2STBY (1 << 13)
134#define VGEN2MODE (1 << 14)
135#define VPLLEN (1 << 15)
136#define VPLLSTBY (1 << 16)
137#define VUSBEN (1 << 18)
138#define VUSBSTBY (1 << 19)
139
Stefano Babiccacdd2b2010-04-18 19:27:44 +0200140/* Reg Mode 1 */
141#define VGEN3EN (1 << 0)
142#define VGEN3STBY (1 << 1)
143#define VGEN3MODE (1 << 2)
144#define VGEN3CONFIG (1 << 3)
145#define VCAMEN (1 << 6)
146#define VCAMSTBY (1 << 7)
147#define VCAMMODE (1 << 8)
148#define VCAMCONFIG (1 << 9)
149#define VVIDEOEN (1 << 12)
150#define VIDEOSTBY (1 << 13)
151#define VVIDEOMODE (1 << 14)
152#define VAUDIOEN (1 << 15)
153#define VAUDIOSTBY (1 << 16)
154#define VSDEN (1 << 18)
155#define VSDSTBY (1 << 19)
156#define VSDMODE (1 << 20)
157
Stefano Babice1b6f592010-07-06 19:32:09 +0200158/* Reg Power Control 2*/
159#define WDIRESET (1 << 12)
160
Liu Hui-R643434cf4cd72011-01-03 22:27:42 +0000161/* SWx Output Volts */
162#define SWX_OUT_MASK 0x1F
163#define SWX_OUT_1_25 0x1A
164#define SWX_OUT_1_30 0X1C
165
Marek Vasut00f3a222011-01-19 04:40:35 +0000166/* Buck Switchers (SW1,2,3,4) Output Voltage */
167/*
168 * NOTE: These values are for SWxHI = 0,
169 * SWxHI = 1 adds 0.5V to the desired voltage
170 */
171#define SWx_0_600V 0
172#define SWx_0_625V 1
173#define SWx_0_650V 2
174#define SWx_0_675V 3
175#define SWx_0_700V 4
176#define SWx_0_725V 5
177#define SWx_0_750V 6
178#define SWx_0_775V 7
179#define SWx_0_800V 8
180#define SWx_0_825V 9
181#define SWx_0_850V 10
182#define SWx_0_875V 11
183#define SWx_0_900V 12
184#define SWx_0_925V 13
185#define SWx_0_950V 14
186#define SWx_0_975V 15
187#define SWx_1_000V 16
188#define SWx_1_025V 17
189#define SWx_1_050V 18
190#define SWx_1_075V 19
191#define SWx_1_100V 20
192#define SWx_1_125V 21
193#define SWx_1_150V 22
194#define SWx_1_175V 23
195#define SWx_1_200V 24
196#define SWx_1_225V 25
197#define SWx_1_250V 26
198#define SWx_1_275V 27
199#define SWx_1_300V 28
200#define SWx_1_325V 29
201#define SWx_1_350V 30
202#define SWx_1_375V 31
203#define SWx_VOLT_MASK 0x1F
204
Stefano Babiccacdd2b2010-04-18 19:27:44 +0200205#endif