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git01.mediatek.com / filogic / uboot / d10297cc6b4bda66486241c66f3a635fb46e546d / . / drivers / gpio / zynqmp_gpio_modepin.c
blob: e9565ff5430e04720748bc2d5ef63d4ef98636a4 [file] [log] [blame]
T Karthik Reddy01719722021-10-29 13:11:43 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ZynqMP GPIO modepin driver
4 *
5 * Copyright (C) 2021 Xilinx, Inc.
6 */
7
8#include <common.h>
9#include <errno.h>
10#include <asm/io.h>
11#include <asm/gpio.h>
12#include <dm.h>
13#include <asm/arch/hardware.h>
14#include <zynqmp_firmware.h>
15
16#define OUTEN(pin) (BIT(0) << (pin))
17#define INVAL(pin) (BIT(4) << (pin))
18#define OUTVAL(pin) (BIT(8) << (pin))
19
20#define ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK 0xF0F
21#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL (ZYNQMP_CRL_APB_BASEADDR + \
22 (0x250U))
23
24static int get_gpio_modepin(u32 *ret_payload)
25{
26 return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
27 0, 0, 0, ret_payload);
28}
29
30static int set_gpio_modepin(int val)
31{
32 return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
33 ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK,
34 val, 0, NULL);
35}
36
37static int modepin_gpio_direction_input(struct udevice *dev,
38 unsigned int offset)
39{
40 return 0;
41}
42
43static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset,
44 int value)
45{
46 u32 ret_payload[PAYLOAD_ARG_CNT];
47 u32 out_val = 0;
48 int ret;
49
50 ret = get_gpio_modepin(ret_payload);
Algapally Santosh Sagarc75f1c42023-01-19 22:36:15 -0700[diff] [blame]51 if (ret)
52 return ret;
53
T Karthik Reddy01719722021-10-29 13:11:43 +0200[diff] [blame]54 if (value)
55 out_val = OUTVAL(offset) | ret_payload[1];
56 else
57 out_val = ~OUTVAL(offset) & ret_payload[1];
58
59 return set_gpio_modepin(out_val);
60}
61
62static int modepin_gpio_direction_output(struct udevice *dev,
63 unsigned int offset, int value)
64{
65 u32 ret_payload[PAYLOAD_ARG_CNT];
66 u32 out_en = 0;
67 int ret;
68
69 ret = get_gpio_modepin(ret_payload);
70 if (ret)
71 return ret;
72
73 if (value)
74 out_en = OUTEN(offset) | ret_payload[1];
75 else
76 out_en = ~OUTEN(offset) & ret_payload[1];
77
78 ret = set_gpio_modepin(out_en);
79 if (ret)
80 return ret;
81
82 return modepin_gpio_set_value(dev, offset, value);
83}
84
85static int modepin_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
86 struct ofnode_phandle_args *args)
87{
88 desc->offset = args->args[0];
89
90 return 0;
91}
92
93static int modepin_gpio_get_value(struct udevice *dev, unsigned int offset)
94{
95 u32 ret_payload[PAYLOAD_ARG_CNT];
96 int ret;
97
98 ret = get_gpio_modepin(ret_payload);
99 if (ret)
100 return ret;
101
102 return (INVAL(offset) & ret_payload[1]) ? 1 : 0;
103}
104
105static int modepin_gpio_get_function(struct udevice *dev, unsigned int offset)
106{
107 u32 ret_payload[PAYLOAD_ARG_CNT];
108 int ret;
109
110 ret = get_gpio_modepin(ret_payload);
111 if (ret)
112 return ret;
113
114 return (OUTEN(offset) & ret_payload[1]) ? GPIOF_OUTPUT : GPIOF_INPUT;
115}
116
117static const struct dm_gpio_ops modepin_gpio_ops = {
118 .direction_input = modepin_gpio_direction_input,
119 .direction_output = modepin_gpio_direction_output,
120 .get_value = modepin_gpio_get_value,
121 .set_value = modepin_gpio_set_value,
122 .get_function = modepin_gpio_get_function,
123 .xlate = modepin_gpio_xlate,
124};
125
126static int modepin_gpio_probe(struct udevice *dev)
127{
128 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
129 const void *label_ptr;
130
131 label_ptr = dev_read_prop(dev, "label", NULL);
132 if (label_ptr) {
133 uc_priv->bank_name = strdup(label_ptr);
134 if (!uc_priv->bank_name)
135 return -ENOMEM;
136 } else {
137 uc_priv->bank_name = dev->name;
138 }
139
140 uc_priv->gpio_count = 4;
141
142 return 0;
143}
144
145static const struct udevice_id modepin_gpio_ids[] = {
146 { .compatible = "xlnx,zynqmp-gpio-modepin",},
147 { }
148};
149
150U_BOOT_DRIVER(modepin_gpio) = {
151 .name = "modepin_gpio",
152 .id = UCLASS_GPIO,
153 .ops = &modepin_gpio_ops,
154 .of_match = modepin_gpio_ids,
155 .probe = modepin_gpio_probe,
156};