| Sean Anderson | 4d88d96 | 2020-06-24 06:41:11 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> |
| 4 | */ |
| 5 | |
| 6 | #ifndef K210_SYSCTL_H |
| 7 | #define K210_SYSCTL_H |
| 8 | |
| 9 | /* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */ |
| 10 | #define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ |
| 11 | #define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ |
| 12 | #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ |
| 13 | #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ |
| 14 | #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ |
| 15 | #define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ |
| 16 | #define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ |
| 17 | #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ |
| 18 | #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ |
| 19 | #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ |
| 20 | #define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ |
| 21 | #define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ |
| 22 | #define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ |
| 23 | #define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ |
| 24 | #define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ |
| 25 | #define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ |
| 26 | #define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ |
| 27 | #define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ |
| 28 | #define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ |
| 29 | #define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ |
| 30 | #define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ |
| 31 | #define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ |
| 32 | #define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ |
| 33 | #define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ |
| 34 | #define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ |
| 35 | #define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ |
| 36 | #define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ |
| 37 | |
| 38 | #endif /* K210_SYSCTL_H */ |