| Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 1 | MIPS Boston Development Board |
| 2 | |
| 3 | --------- |
| 4 | About |
| 5 | --------- |
| 6 | |
| 7 | The MIPS Boston development board is built around an FPGA & 3 PCIe controllers, |
| 8 | one of which is connected to an Intel EG20T Platform Controller Hub which |
| 9 | provides most connectivity to the board. It is used during the development & |
| 10 | testing of both new CPUs and the software support for them. It is essentially |
| 11 | the successor of the older MIPS Malta board. |
| 12 | |
| 13 | -------- |
| 14 | QEMU |
| 15 | -------- |
| 16 | |
| 17 | U-Boot can be run on a currently out-of-tree branch of QEMU with support for |
| 18 | the Boston board added. This QEMU code can currently be found in the "boston" |
| 19 | branch of git://git.linux-mips.org/pub/scm/paul/qemu.git and used like so: |
| 20 | |
| 21 | $ git clone git://git.linux-mips.org/pub/scm/paul/qemu.git -b boston |
| 22 | $ cd qemu |
| 23 | $ ./configure --target-list=mips64el-softmmu |
| 24 | $ make |
| 25 | $ ./mips64el-softmmu/qemu-system-mips64el -M boston -m 2G \ |
| 26 | -bios u-boot.bin -serial stdio |
| 27 | |
| 28 | Please note that QEMU will default to emulating the I6400 CPU which implements |
| 29 | the MIPS64r6 ISA, and at the time of writing doesn't implement any earlier CPUs |
| 30 | with support for the CPS features the Boston board relies upon. You will |
| 31 | therefore need to configure U-Boot to build for MIPSr6 in order to obtain a |
| 32 | binary that will work in QEMU. |
| 33 | |
| 34 | ------------- |
| 35 | Toolchain |
| 36 | ------------- |
| 37 | |
| 38 | If building for MIPSr6 then you will need a toolchain including GCC 5.x or |
| 39 | newer, or the Codescape toolchain available for download from Imagination |
| 40 | Technologies: |
| 41 | |
| 42 | http://codescape-mips-sdk.imgtec.com/components/toolchain/2015.06-05/ |
| 43 | |
| 44 | The "IMG GNU Linux Toolchain" is capable of building for all current MIPS ISAs, |
| 45 | architecture revisions & both endiannesses. |
| 46 | |
| 47 | -------- |
| 48 | TODO |
| 49 | -------- |
| 50 | |
| 51 | - AHCI support |
| 52 | - CPU driver |
| 53 | - Exception handling (+UHI?) |
| 54 | - Flash support |
| 55 | - IOCU support |
| 56 | - L2 cache support |
| 57 | - More general LCD display driver |
| 58 | - Multi-arch-variant multi-endian fat binary |