Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Philipp Tomsich | 1a18f30 | 2017-05-31 17:59:31 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH |
| 4 | * Copyright (c) 2015 Google, Inc |
| 5 | * Copyright 2014 Rockchip Inc. |
Philipp Tomsich | 1a18f30 | 2017-05-31 17:59:31 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <display.h> |
| 10 | #include <dm.h> |
| 11 | #include <regmap.h> |
| 12 | #include <video.h> |
| 13 | #include <asm/hardware.h> |
| 14 | #include <asm/io.h> |
| 15 | #include "rk_vop.h" |
| 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
| 19 | static void rk3399_set_pin_polarity(struct udevice *dev, |
| 20 | enum vop_modes mode, u32 polarity) |
| 21 | { |
| 22 | struct rk_vop_priv *priv = dev_get_priv(dev); |
| 23 | struct rk3288_vop *regs = priv->regs; |
| 24 | |
| 25 | /* |
| 26 | * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of |
| 27 | * the polarity configuration (in ctrl1). |
| 28 | */ |
| 29 | switch (mode) { |
| 30 | case VOP_MODE_HDMI: |
| 31 | clrsetbits_le32(®s->dsp_ctrl1, |
| 32 | M_RK3399_DSP_HDMI_POL, |
| 33 | V_RK3399_DSP_HDMI_POL(polarity)); |
| 34 | break; |
| 35 | |
| 36 | case VOP_MODE_EDP: |
| 37 | clrsetbits_le32(®s->dsp_ctrl1, |
| 38 | M_RK3399_DSP_EDP_POL, |
| 39 | V_RK3399_DSP_EDP_POL(polarity)); |
| 40 | break; |
| 41 | |
| 42 | case VOP_MODE_MIPI: |
| 43 | clrsetbits_le32(®s->dsp_ctrl1, |
| 44 | M_RK3399_DSP_MIPI_POL, |
| 45 | V_RK3399_DSP_MIPI_POL(polarity)); |
| 46 | break; |
| 47 | |
| 48 | case VOP_MODE_LVDS: |
| 49 | /* The RK3399 has neither parallel RGB nor LVDS output. */ |
| 50 | default: |
| 51 | debug("%s: unsupported output mode %x\n", __func__, mode); |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Try some common regulators. We should really get these from the |
| 57 | * device tree somehow. |
| 58 | */ |
| 59 | static const char * const rk3399_regulator_names[] = { |
| 60 | "vcc33_lcd" |
| 61 | }; |
| 62 | |
| 63 | static int rk3399_vop_probe(struct udevice *dev) |
| 64 | { |
| 65 | /* Before relocation we don't need to do anything */ |
| 66 | if (!(gd->flags & GD_FLG_RELOC)) |
| 67 | return 0; |
| 68 | |
| 69 | /* Probe regulators required for the RK3399 VOP */ |
| 70 | rk_vop_probe_regulators(dev, rk3399_regulator_names, |
| 71 | ARRAY_SIZE(rk3399_regulator_names)); |
| 72 | |
| 73 | return rk_vop_probe(dev); |
| 74 | } |
| 75 | |
| 76 | struct rkvop_driverdata rk3399_lit_driverdata = { |
| 77 | .set_pin_polarity = rk3399_set_pin_polarity, |
| 78 | }; |
| 79 | |
| 80 | struct rkvop_driverdata rk3399_big_driverdata = { |
| 81 | .features = VOP_FEATURE_OUTPUT_10BIT, |
| 82 | .set_pin_polarity = rk3399_set_pin_polarity, |
| 83 | }; |
| 84 | |
| 85 | static const struct udevice_id rk3399_vop_ids[] = { |
| 86 | { .compatible = "rockchip,rk3399-vop-big", |
| 87 | .data = (ulong)&rk3399_big_driverdata }, |
| 88 | { .compatible = "rockchip,rk3399-vop-lit", |
| 89 | .data = (ulong)&rk3399_lit_driverdata }, |
| 90 | { } |
| 91 | }; |
| 92 | |
| 93 | static const struct video_ops rk3399_vop_ops = { |
| 94 | }; |
| 95 | |
| 96 | U_BOOT_DRIVER(rk3399_vop) = { |
| 97 | .name = "rk3399_vop", |
| 98 | .id = UCLASS_VIDEO, |
| 99 | .of_match = rk3399_vop_ids, |
| 100 | .ops = &rk3399_vop_ops, |
| 101 | .bind = rk_vop_bind, |
| 102 | .probe = rk3399_vop_probe, |
| 103 | .priv_auto_alloc_size = sizeof(struct rk_vop_priv), |
| 104 | }; |