| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | d50f905 | 2011-01-27 10:58:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010,2011 | ||||
| 4 | * NVIDIA Corporation <www.nvidia.com> | ||||
| Tom Warren | d50f905 | 2011-01-27 10:58:08 +0000 | [diff] [blame] | 5 | */ |
| 6 | |||||
| 7 | #ifndef __CONFIG_H | ||||
| 8 | #define __CONFIG_H | ||||
| 9 | |||||
| Alexey Brodkin | 267d8e2 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 10 | #include <linux/sizes.h> |
| Simon Glass | ef2fb1a | 2012-04-02 13:19:03 +0000 | [diff] [blame] | 11 | |
| Allen Martin | 55d98a1 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 12 | #include "tegra20-common.h" |
| Tom Warren | d50f905 | 2011-01-27 10:58:08 +0000 | [diff] [blame] | 13 | |
| 14 | /* High-level configuration options */ | ||||
| Tom Rini | ca2e1a5 | 2022-12-04 10:13:58 -0500 | [diff] [blame] | 15 | #define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" |
| Tom Warren | d50f905 | 2011-01-27 10:58:08 +0000 | [diff] [blame] | 16 | |
| 17 | /* Board-specific serial config */ | ||||
| Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 18 | #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE |
| Tom Warren | d50f905 | 2011-01-27 10:58:08 +0000 | [diff] [blame] | 19 | |
| Stephen Warren | ade0d5c | 2012-05-24 11:38:39 +0000 | [diff] [blame] | 20 | /* Environment in eMMC, at the end of 2nd "boot sector" */ |
| Simon Glass | 3e094a8 | 2012-02-27 10:52:52 +0000 | [diff] [blame] | 21 | |
| Simon Glass | bad90ee | 2012-07-29 20:53:30 +0000 | [diff] [blame] | 22 | /* NAND support */ |
| Simon Glass | bad90ee | 2012-07-29 20:53:30 +0000 | [diff] [blame] | 23 | |
| 24 | /* Max number of NAND devices */ | ||||
| Simon Glass | 3e7b329 | 2012-11-05 13:21:01 +0000 | [diff] [blame] | 25 | |
| 26 | #include "tegra-common-post.h" | ||||
| 27 | |||||
| Tom Warren | d50f905 | 2011-01-27 10:58:08 +0000 | [diff] [blame] | 28 | #endif /* __CONFIG_H */ |