blob: 008c7257c4328c9e5b47a2cb99d1160c63671b12 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
jason56ef75c2013-11-06 22:59:08 +08002/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liewdd8513c2008-07-23 17:11:47 -05003 * Hayden Fraser (Hayden.Fraser@freescale.com)
TsiChung Liewdd8513c2008-07-23 17:11:47 -05004 */
5
6#ifndef _M5253DEMO_H
7#define _M5253DEMO_H
8
Simon Glassfb64e362020-05-10 11:40:09 -06009#include <linux/stringify.h>
10
Tom Rini6a5dccc2022-11-16 13:10:41 -050011#define CFG_SYS_UART_PORT (0)
TsiChung Liewdd8513c2008-07-23 17:11:47 -050012
TsiChung Liewdd8513c2008-07-23 17:11:47 -050013
14/* Configuration for environment
15 * Environment is embedded in u-boot in the second sector of the flash
16 */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050017
angelo@sysam.it6312a952015-03-29 22:54:16 +020018#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060019 . = DEFINED(env_offset) ? env_offset : .; \
20 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +020021
TsiChung Liewdd8513c2008-07-23 17:11:47 -050022#ifdef CONFIG_DRIVER_DM9000
Tom Rinic9edebe2022-12-04 10:03:50 -050023# define CFG_EXTRA_ENV_SETTINGS \
TsiChung Liewdd8513c2008-07-23 17:11:47 -050024 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +020025 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liewdd8513c2008-07-23 17:11:47 -050026 "loadaddr=10000\0" \
27 "u-boot=u-boot.bin\0" \
28 "load=tftp ${loadaddr) ${u-boot}\0" \
29 "upd=run load; run prog\0" \
TsiChung Liew3dd72f62010-03-10 11:56:36 -060030 "prog=prot off 0xff800000 0xff82ffff;" \
31 "era 0xff800000 0xff82ffff;" \
TsiChung Liew0212f742010-03-15 19:39:21 -050032 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
TsiChung Liewdd8513c2008-07-23 17:11:47 -050033 "save\0" \
34 ""
35#endif
36
TsiChung Liew0c1e3252008-08-19 03:01:19 +060037/* I2C */
Tom Rini6a5dccc2022-11-16 13:10:41 -050038#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C))
39#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
40#define CFG_SYS_I2C_PINMUX_SET (0)
TsiChung Liew0c1e3252008-08-19 03:01:19 +060041
Tom Rini6a5dccc2022-11-16 13:10:41 -050042#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
43#define CFG_SYS_FAST_CLK
44#ifdef CFG_SYS_FAST_CLK
45# define CFG_SYS_PLLCR 0x1243E054
46# define CFG_SYS_CLK 140000000
TsiChung Liewdd8513c2008-07-23 17:11:47 -050047#else
Tom Rini6a5dccc2022-11-16 13:10:41 -050048# define CFG_SYS_PLLCR 0x135a4140
49# define CFG_SYS_CLK 70000000
TsiChung Liewdd8513c2008-07-23 17:11:47 -050050#endif
51
52/*
53 * Low Level Configuration Settings
54 * (address mappings, register initial values, etc.)
55 * You should know what you are doing if you make changes here.
56 */
57
Tom Rini6a5dccc2022-11-16 13:10:41 -050058#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
59#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050060
61/*
62 * Definitions for initial stack pointer and data area (in DPRAM)
63 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050064#define CFG_SYS_INIT_RAM_ADDR 0x20000000
65#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050066
67/*
68 * Start addresses for the final memory configuration
69 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050070 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewdd8513c2008-07-23 17:11:47 -050071 */
Tom Rinibb4dd962022-11-16 13:10:37 -050072#define CFG_SYS_SDRAM_BASE 0x00000000
73#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050074
TsiChung Liewdd8513c2008-07-23 17:11:47 -050075/*
76 * For booting Linux, the board info and command line data
77 * have to be in the first 8 MB of memory, since this is
78 * the maximum mapped by the Linux kernel during initialization ??
79 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050080#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
TsiChung Liewdd8513c2008-07-23 17:11:47 -050081
82/* FLASH organization */
Tom Rini6a5dccc2022-11-16 13:10:41 -050083#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
TsiChung Liewdd8513c2008-07-23 17:11:47 -050084
85#define FLASH_SST6401B 0x200
86#define SST_ID_xF6401B 0x236D236D
87
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liewdd8513c2008-07-23 17:11:47 -050089/*
90 * Unable to use CFI driver, due to incompatible sector erase command by SST.
91 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
92 * 0x30 is block erase in SST
93 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050094# define CFG_SYS_FLASH_SIZE 0x800000
TsiChung Liewdd8513c2008-07-23 17:11:47 -050095#else
Tom Rini6a5dccc2022-11-16 13:10:41 -050096# define CFG_SYS_SST_SECT 2048
97# define CFG_SYS_SST_SECTSZ 0x1000
TsiChung Liewdd8513c2008-07-23 17:11:47 -050098#endif
99
100/* Cache Configuration */
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500101
Tom Rini6a5dccc2022-11-16 13:10:41 -0500102#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
103 CFG_SYS_INIT_RAM_SIZE - 8)
104#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
105 CFG_SYS_INIT_RAM_SIZE - 4)
106#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
107#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600108 CF_ADDRMASK(8) | \
109 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500110#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -0500111 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600112 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500113#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600114 CF_CACR_DBWE)
115
Tom Rini6a5dccc2022-11-16 13:10:41 -0500116#define CFG_SYS_CS0_BASE 0xFF800000
117#define CFG_SYS_CS0_MASK 0x007F0021
118#define CFG_SYS_CS0_CTRL 0x00001D80
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500119
Tom Rini6a5dccc2022-11-16 13:10:41 -0500120#define CFG_SYS_CS1_BASE 0xE0000000
121#define CFG_SYS_CS1_MASK 0x00000001
122#define CFG_SYS_CS1_CTRL 0x00003DD8
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500123
124/*-----------------------------------------------------------------------
125 * Port configuration
126 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500127#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
128#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
129#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
130#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
131#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
132#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
133#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500134
Angelo Dureghello49becce2023-02-25 23:25:26 +0100135#define CFG_MCFTMR
136
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500137#endif /* _M5253DEMO_H */