Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
jason | 56ef75c | 2013-11-06 22:59:08 +0800 | [diff] [blame] | 2 | /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 3 | * Hayden Fraser (Hayden.Fraser@freescale.com) |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _M5253DEMO_H |
| 7 | #define _M5253DEMO_H |
| 8 | |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 9 | #include <linux/stringify.h> |
| 10 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 11 | #define CFG_SYS_UART_PORT (0) |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 12 | |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 13 | |
| 14 | /* Configuration for environment |
| 15 | * Environment is embedded in u-boot in the second sector of the flash |
| 16 | */ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 17 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 18 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 19 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 20 | env/embedded.o(.text*); |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 21 | |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 22 | #ifdef CONFIG_DRIVER_DM9000 |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 23 | # define CFG_EXTRA_ENV_SETTINGS \ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 24 | "netdev=eth0\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 25 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 26 | "loadaddr=10000\0" \ |
| 27 | "u-boot=u-boot.bin\0" \ |
| 28 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 29 | "upd=run load; run prog\0" \ |
TsiChung Liew | 3dd72f6 | 2010-03-10 11:56:36 -0600 | [diff] [blame] | 30 | "prog=prot off 0xff800000 0xff82ffff;" \ |
| 31 | "era 0xff800000 0xff82ffff;" \ |
TsiChung Liew | 0212f74 | 2010-03-15 19:39:21 -0500 | [diff] [blame] | 32 | "cp.b ${loadaddr} 0xff800000 ${filesize};" \ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 33 | "save\0" \ |
| 34 | "" |
| 35 | #endif |
| 36 | |
TsiChung Liew | 0c1e325 | 2008-08-19 03:01:19 +0600 | [diff] [blame] | 37 | /* I2C */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 38 | #define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) |
| 39 | #define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) |
| 40 | #define CFG_SYS_I2C_PINMUX_SET (0) |
TsiChung Liew | 0c1e325 | 2008-08-19 03:01:19 +0600 | [diff] [blame] | 41 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 42 | #undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
| 43 | #define CFG_SYS_FAST_CLK |
| 44 | #ifdef CFG_SYS_FAST_CLK |
| 45 | # define CFG_SYS_PLLCR 0x1243E054 |
| 46 | # define CFG_SYS_CLK 140000000 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 47 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 48 | # define CFG_SYS_PLLCR 0x135a4140 |
| 49 | # define CFG_SYS_CLK 70000000 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 50 | #endif |
| 51 | |
| 52 | /* |
| 53 | * Low Level Configuration Settings |
| 54 | * (address mappings, register initial values, etc.) |
| 55 | * You should know what you are doing if you make changes here. |
| 56 | */ |
| 57 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 58 | #define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
| 59 | #define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 60 | |
| 61 | /* |
| 62 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 63 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 64 | #define CFG_SYS_INIT_RAM_ADDR 0x20000000 |
| 65 | #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 66 | |
| 67 | /* |
| 68 | * Start addresses for the final memory configuration |
| 69 | * (Set up by the startup code) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 70 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 71 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 72 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
| 73 | #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 74 | |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 75 | /* |
| 76 | * For booting Linux, the board info and command line data |
| 77 | * have to be in the first 8 MB of memory, since this is |
| 78 | * the maximum mapped by the Linux kernel during initialization ?? |
| 79 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 80 | #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 81 | |
| 82 | /* FLASH organization */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 83 | #define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 84 | |
| 85 | #define FLASH_SST6401B 0x200 |
| 86 | #define SST_ID_xF6401B 0x236D236D |
| 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #ifdef CONFIG_SYS_FLASH_CFI |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 89 | /* |
| 90 | * Unable to use CFI driver, due to incompatible sector erase command by SST. |
| 91 | * Amd/Atmel use 0x30 for sector erase, SST use 0x50. |
| 92 | * 0x30 is block erase in SST |
| 93 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 94 | # define CFG_SYS_FLASH_SIZE 0x800000 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 95 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 96 | # define CFG_SYS_SST_SECT 2048 |
| 97 | # define CFG_SYS_SST_SECTSZ 0x1000 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 98 | #endif |
| 99 | |
| 100 | /* Cache Configuration */ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 101 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 102 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 103 | CFG_SYS_INIT_RAM_SIZE - 8) |
| 104 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 105 | CFG_SYS_INIT_RAM_SIZE - 4) |
| 106 | #define CFG_SYS_ICACHE_INV (CF_CACR_DCM) |
| 107 | #define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 108 | CF_ADDRMASK(8) | \ |
| 109 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 110 | #define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 111 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 112 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 113 | #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 114 | CF_CACR_DBWE) |
| 115 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 116 | #define CFG_SYS_CS0_BASE 0xFF800000 |
| 117 | #define CFG_SYS_CS0_MASK 0x007F0021 |
| 118 | #define CFG_SYS_CS0_CTRL 0x00001D80 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 119 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 120 | #define CFG_SYS_CS1_BASE 0xE0000000 |
| 121 | #define CFG_SYS_CS1_MASK 0x00000001 |
| 122 | #define CFG_SYS_CS1_CTRL 0x00003DD8 |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 123 | |
| 124 | /*----------------------------------------------------------------------- |
| 125 | * Port configuration |
| 126 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 127 | #define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
| 128 | #define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ |
| 129 | #define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ |
| 130 | #define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
| 131 | #define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
| 132 | #define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
| 133 | #define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 134 | |
Angelo Dureghello | 49becce | 2023-02-25 23:25:26 +0100 | [diff] [blame] | 135 | #define CFG_MCFTMR |
| 136 | |
TsiChung Liew | dd8513c | 2008-07-23 17:11:47 -0500 | [diff] [blame] | 137 | #endif /* _M5253DEMO_H */ |