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git01.mediatek.com / filogic / uboot / cdfde798babc9cb7eee50c8008d81a80eef1e450 / . / arch / arm / dts / imx8mp-verdin.dtsi
blob: 7b712d1888eadfc6e4eb60282bc6cb3ddc32f9f9 [file] [log] [blame]
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "dt-bindings/pwm/pwm.h"
7#include "imx8mp.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart3;
12 };
13
14 aliases {
15 /* Ethernet aliases to ensure correct MAC addresses */
16 ethernet0 = &eqos;
17 ethernet1 = &fec;
18 rtc0 = &rtc_i2c;
19 rtc1 = &snvs_rtc;
20 };
21
22 backlight: backlight {
23 compatible = "pwm-backlight";
24 brightness-levels = <0 45 63 88 119 158 203 255>;
25 default-brightness-level = <4>;
26 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
27 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
30 power-supply = <&reg_3p3v>;
31 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
32 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
33 status = "disabled";
34 };
35
36 backlight_mezzanine: backlight-mezzanine {
37 compatible = "pwm-backlight";
38 brightness-levels = <0 45 63 88 119 158 203 255>;
39 default-brightness-level = <4>;
40 /* Verdin GPIO 4 (SODIMM 212) */
41 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
42 /* Verdin PWM_2 (SODIMM 16) */
43 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
44 status = "disabled";
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_gpio_keys>;
51
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame^]52 button-wakeup {
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]53 debounce-interval = <10>;
54 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
56 label = "Wake-Up";
57 linux,code = <KEY_WAKEUP>;
58 wakeup-source;
59 };
60 };
61
62 /* Carrier Board Supplies */
63 reg_1p8v: regulator-1p8v {
64 compatible = "regulator-fixed";
65 regulator-max-microvolt = <1800000>;
66 regulator-min-microvolt = <1800000>;
67 regulator-name = "+V1.8_SW";
68 };
69
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-max-microvolt = <3300000>;
73 regulator-min-microvolt = <3300000>;
74 regulator-name = "+V3.3_SW";
75 };
76
77 reg_5p0v: regulator-5p0v {
78 compatible = "regulator-fixed";
79 regulator-max-microvolt = <5000000>;
80 regulator-min-microvolt = <5000000>;
81 regulator-name = "+V5_SW";
82 };
83
84 /* Non PMIC On-module Supplies */
85 reg_module_eth1phy: regulator-module-eth1phy {
86 compatible = "regulator-fixed";
87 enable-active-high;
88 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
89 off-on-delay = <500000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_reg_eth>;
92 regulator-always-on;
93 regulator-boot-on;
94 regulator-max-microvolt = <3300000>;
95 regulator-min-microvolt = <3300000>;
96 regulator-name = "On-module +V3.3_ETH";
97 startup-delay-us = <200000>;
98 vin-supply = <&reg_vdd_3v3>;
99 };
100
101 reg_usb1_vbus: regulator-usb1-vbus {
102 compatible = "regulator-fixed";
103 enable-active-high;
104 /* Verdin USB_1_EN (SODIMM 155) */
105 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_usb1_vbus>;
108 regulator-max-microvolt = <5000000>;
109 regulator-min-microvolt = <5000000>;
110 regulator-name = "USB_1_EN";
111 };
112
113 reg_usb2_vbus: regulator-usb2-vbus {
114 compatible = "regulator-fixed";
115 enable-active-high;
116 /* Verdin USB_2_EN (SODIMM 185) */
117 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_usb2_vbus>;
120 regulator-max-microvolt = <5000000>;
121 regulator-min-microvolt = <5000000>;
122 regulator-name = "USB_2_EN";
123 };
124
125 reg_usdhc2_vmmc: regulator-usdhc2 {
126 compatible = "regulator-fixed";
127 enable-active-high;
128 /* Verdin SD_1_PWR_EN (SODIMM 76) */
129 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
130 off-on-delay = <100000>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
133 regulator-max-microvolt = <3300000>;
134 regulator-min-microvolt = <3300000>;
135 regulator-name = "+V3.3_SD";
136 startup-delay-us = <2000>;
137 };
138
139 reserved-memory {
140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 /* Use the kernel configuration settings instead */
145 /delete-node/ linux,cma;
146 };
147};
148
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame^]149&A53_0 {
150 cpu-supply = <&reg_vdd_arm>;
151};
152
153&A53_1 {
154 cpu-supply = <&reg_vdd_arm>;
155};
156
157&A53_2 {
158 cpu-supply = <&reg_vdd_arm>;
159};
160
161&A53_3 {
162 cpu-supply = <&reg_vdd_arm>;
163};
164
165&cpu_alert0 {
166 temperature = <95000>;
167};
168
169&cpu_crit0 {
170 temperature = <105000>;
171};
172
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]173/* Verdin SPI_1 */
174&ecspi1 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_ecspi1>;
180};
181
182/* Verdin ETH_1 (On-module PHY) */
183&eqos {
184 phy-handle = <&ethphy0>;
185 phy-mode = "rgmii-id";
186 phy-supply = <&reg_module_eth1phy>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_eqos>;
189 snps,force_thresh_dma_mode;
190 snps,mtl-rx-config = <&mtl_rx_setup>;
191 snps,mtl-tx-config = <&mtl_tx_setup>;
192
193 mdio {
194 compatible = "snps,dwmac-mdio";
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 ethphy0: ethernet-phy@7 {
199 compatible = "ethernet-phy-ieee802.3-c22";
200 eee-broken-100tx;
201 eee-broken-1000t;
202 interrupt-parent = <&gpio1>;
203 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
204 micrel,led-mode = <0>;
205 reg = <7>;
206 };
207 };
208
209 mtl_rx_setup: rx-queues-config {
210 snps,rx-queues-to-use = <5>;
211 snps,rx-sched-sp;
212
213 queue0 {
214 snps,dcb-algorithm;
215 snps,priority = <0x1>;
216 snps,map-to-dma-channel = <0>;
217 };
218
219 queue1 {
220 snps,dcb-algorithm;
221 snps,priority = <0x2>;
222 snps,map-to-dma-channel = <1>;
223 };
224
225 queue2 {
226 snps,dcb-algorithm;
227 snps,priority = <0x4>;
228 snps,map-to-dma-channel = <2>;
229 };
230
231 queue3 {
232 snps,dcb-algorithm;
233 snps,priority = <0x8>;
234 snps,map-to-dma-channel = <3>;
235 };
236
237 queue4 {
238 snps,dcb-algorithm;
239 snps,priority = <0xf0>;
240 snps,map-to-dma-channel = <4>;
241 };
242 };
243
244 mtl_tx_setup: tx-queues-config {
245 snps,tx-queues-to-use = <5>;
246 snps,tx-sched-sp;
247
248 queue0 {
249 snps,dcb-algorithm;
250 snps,priority = <0x1>;
251 };
252
253 queue1 {
254 snps,dcb-algorithm;
255 snps,priority = <0x2>;
256 };
257
258 queue2 {
259 snps,dcb-algorithm;
260 snps,priority = <0x4>;
261 };
262
263 queue3 {
264 snps,dcb-algorithm;
265 snps,priority = <0x8>;
266 };
267
268 queue4 {
269 snps,dcb-algorithm;
270 snps,priority = <0xf0>;
271 };
272 };
273};
274
275/* Verdin ETH_2_RGMII */
276&fec {
277 fsl,magic-packet;
278 phy-handle = <&ethphy1>;
279 phy-mode = "rgmii-id";
280 pinctrl-names = "default", "sleep";
281 pinctrl-0 = <&pinctrl_fec>;
282 pinctrl-1 = <&pinctrl_fec_sleep>;
283
284 mdio {
285 #address-cells = <1>;
286 #size-cells = <0>;
287
288 ethphy1: ethernet-phy@7 {
289 compatible = "ethernet-phy-ieee802.3-c22";
290 interrupt-parent = <&gpio4>;
291 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
292 micrel,led-mode = <0>;
293 reg = <7>;
294 };
295 };
296};
297
298/* Verdin CAN_1 */
299&flexcan1 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_flexcan1>;
302 status = "disabled";
303};
304
305/* Verdin CAN_2 */
306&flexcan2 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_flexcan2>;
309 status = "disabled";
310};
311
312/* Verdin QSPI_1 */
313&flexspi {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_flexspi0>;
316};
317
318&gpio1 {
319 gpio-line-names = "SODIMM_206",
320 "SODIMM_208",
321 "",
322 "",
323 "",
324 "SODIMM_210",
325 "SODIMM_212",
326 "SODIMM_216",
327 "SODIMM_218",
328 "",
329 "",
330 "SODIMM_16",
331 "SODIMM_155",
332 "SODIMM_157",
333 "SODIMM_185",
334 "SODIMM_91";
335};
336
337&gpio2 {
338 gpio-line-names = "",
339 "",
340 "",
341 "",
342 "",
343 "",
344 "SODIMM_143",
345 "SODIMM_141",
346 "",
347 "",
348 "SODIMM_161",
349 "",
350 "SODIMM_84",
351 "SODIMM_78",
352 "SODIMM_74",
353 "SODIMM_80",
354 "SODIMM_82",
355 "SODIMM_70",
356 "SODIMM_72";
357
358 ctrl-sleep-moci-hog {
359 gpio-hog;
360 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
361 gpios = <29 GPIO_ACTIVE_HIGH>;
362 line-name = "CTRL_SLEEP_MOCI#";
363 output-high;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
366 };
367};
368
369&gpio3 {
370 gpio-line-names = "SODIMM_52",
371 "SODIMM_54",
372 "",
373 "",
374 "",
375 "",
376 "SODIMM_56",
377 "SODIMM_58",
378 "SODIMM_60",
379 "SODIMM_62",
380 "",
381 "",
382 "",
383 "",
384 "SODIMM_66",
385 "",
386 "SODIMM_64",
387 "",
388 "",
389 "SODIMM_34",
390 "SODIMM_19",
391 "",
392 "SODIMM_32",
393 "",
394 "",
395 "SODIMM_30",
396 "SODIMM_59",
397 "SODIMM_57",
398 "SODIMM_63",
399 "SODIMM_61";
400};
401
402&gpio4 {
403 gpio-line-names = "SODIMM_252",
404 "SODIMM_222",
405 "SODIMM_36",
406 "SODIMM_220",
407 "SODIMM_193",
408 "SODIMM_191",
409 "SODIMM_201",
410 "SODIMM_203",
411 "SODIMM_205",
412 "SODIMM_207",
413 "SODIMM_199",
414 "SODIMM_197",
415 "SODIMM_221",
416 "SODIMM_219",
417 "SODIMM_217",
418 "SODIMM_215",
419 "SODIMM_211",
420 "SODIMM_213",
421 "SODIMM_189",
422 "SODIMM_244",
423 "SODIMM_38",
424 "",
425 "SODIMM_76",
426 "SODIMM_135",
427 "SODIMM_133",
428 "SODIMM_17",
429 "SODIMM_24",
430 "SODIMM_26",
431 "SODIMM_21",
432 "SODIMM_256",
433 "SODIMM_48",
434 "SODIMM_44";
435};
436
437/* On-module I2C */
438&i2c1 {
439 clock-frequency = <400000>;
440 pinctrl-names = "default", "gpio";
441 pinctrl-0 = <&pinctrl_i2c1>;
442 pinctrl-1 = <&pinctrl_i2c1_gpio>;
443 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
444 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
445 status = "okay";
446
447 pca9450: pmic@25 {
448 compatible = "nxp,pca9450c";
449 interrupt-parent = <&gpio1>;
450 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
451 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_pmic>;
454 reg = <0x25>;
455 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
456
457 /*
458 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
459 * I2C level shifter for the TLA2024 ADC behind this PMIC.
460 */
461
462 regulators {
463 BUCK1 {
464 regulator-always-on;
465 regulator-boot-on;
466 regulator-max-microvolt = <1000000>;
467 regulator-min-microvolt = <720000>;
468 regulator-name = "On-module +VDD_SOC (BUCK1)";
469 regulator-ramp-delay = <3125>;
470 };
471
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame^]472 reg_vdd_arm: BUCK2 {
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]473 nxp,dvs-run-voltage = <950000>;
474 nxp,dvs-standby-voltage = <850000>;
475 regulator-always-on;
476 regulator-boot-on;
477 regulator-max-microvolt = <1025000>;
478 regulator-min-microvolt = <720000>;
479 regulator-name = "On-module +VDD_ARM (BUCK2)";
480 regulator-ramp-delay = <3125>;
481 };
482
483 reg_vdd_3v3: BUCK4 {
484 regulator-always-on;
485 regulator-boot-on;
486 regulator-max-microvolt = <3300000>;
487 regulator-min-microvolt = <3300000>;
488 regulator-name = "On-module +V3.3 (BUCK4)";
489 };
490
491 reg_vdd_1v8: BUCK5 {
492 regulator-always-on;
493 regulator-boot-on;
494 regulator-max-microvolt = <1800000>;
495 regulator-min-microvolt = <1800000>;
496 regulator-name = "PWR_1V8_MOCI (BUCK5)";
497 };
498
499 BUCK6 {
500 regulator-always-on;
501 regulator-boot-on;
502 regulator-max-microvolt = <1155000>;
503 regulator-min-microvolt = <1045000>;
504 regulator-name = "On-module +VDD_DDR (BUCK6)";
505 };
506
507 LDO1 {
508 regulator-always-on;
509 regulator-boot-on;
510 regulator-max-microvolt = <1950000>;
511 regulator-min-microvolt = <1650000>;
512 regulator-name = "On-module +V1.8_SNVS (LDO1)";
513 };
514
515 LDO2 {
516 regulator-always-on;
517 regulator-boot-on;
518 regulator-max-microvolt = <1150000>;
519 regulator-min-microvolt = <800000>;
520 regulator-name = "On-module +V0.8_SNVS (LDO2)";
521 };
522
523 LDO3 {
524 regulator-always-on;
525 regulator-boot-on;
526 regulator-max-microvolt = <1800000>;
527 regulator-min-microvolt = <1800000>;
528 regulator-name = "On-module +V1.8A (LDO3)";
529 };
530
531 LDO4 {
532 regulator-always-on;
533 regulator-boot-on;
534 regulator-max-microvolt = <3300000>;
535 regulator-min-microvolt = <3300000>;
536 regulator-name = "On-module +V3.3_ADC (LDO4)";
537 };
538
539 LDO5 {
540 regulator-max-microvolt = <3300000>;
541 regulator-min-microvolt = <1800000>;
542 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
543 };
544 };
545 };
546
547 rtc_i2c: rtc@32 {
548 compatible = "epson,rx8130";
549 reg = <0x32>;
550 };
551
552 /* On-module temperature sensor */
553 hwmon_temp_module: sensor@48 {
554 compatible = "ti,tmp1075";
555 reg = <0x48>;
556 vs-supply = <&reg_vdd_1v8>;
557 };
558
559 adc@49 {
560 compatible = "ti,ads1015";
561 reg = <0x49>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564
565 /* Verdin I2C_1 (ADC_4 - ADC_3) */
566 channel@0 {
567 reg = <0>;
568 ti,datarate = <4>;
569 ti,gain = <2>;
570 };
571
572 /* Verdin I2C_1 (ADC_4 - ADC_1) */
573 channel@1 {
574 reg = <1>;
575 ti,datarate = <4>;
576 ti,gain = <2>;
577 };
578
579 /* Verdin I2C_1 (ADC_3 - ADC_1) */
580 channel@2 {
581 reg = <2>;
582 ti,datarate = <4>;
583 ti,gain = <2>;
584 };
585
586 /* Verdin I2C_1 (ADC_2 - ADC_1) */
587 channel@3 {
588 reg = <3>;
589 ti,datarate = <4>;
590 ti,gain = <2>;
591 };
592
593 /* Verdin I2C_1 ADC_4 */
594 channel@4 {
595 reg = <4>;
596 ti,datarate = <4>;
597 ti,gain = <2>;
598 };
599
600 /* Verdin I2C_1 ADC_3 */
601 channel@5 {
602 reg = <5>;
603 ti,datarate = <4>;
604 ti,gain = <2>;
605 };
606
607 /* Verdin I2C_1 ADC_2 */
608 channel@6 {
609 reg = <6>;
610 ti,datarate = <4>;
611 ti,gain = <2>;
612 };
613
614 /* Verdin I2C_1 ADC_1 */
615 channel@7 {
616 reg = <7>;
617 ti,datarate = <4>;
618 ti,gain = <2>;
619 };
620 };
621
622 eeprom@50 {
623 compatible = "st,24c02";
624 pagesize = <16>;
625 reg = <0x50>;
626 };
627};
628
629/* Verdin I2C_2_DSI */
630&i2c2 {
631 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
632 clock-frequency = <10000>;
633 pinctrl-names = "default", "gpio";
634 pinctrl-0 = <&pinctrl_i2c2>;
635 pinctrl-1 = <&pinctrl_i2c2_gpio>;
636 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
637 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
638
639 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
640 compatible = "atmel,maxtouch";
641 /* Verdin GPIO_3 (SODIMM 210) */
642 interrupt-parent = <&gpio1>;
643 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
644 reg = <0x4a>;
645 /* Verdin GPIO_2 (SODIMM 208) */
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame^]646 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]647 status = "disabled";
648 };
649};
650
651/* TODO: Verdin I2C_3_HDMI */
652
653/* Verdin I2C_4_CSI */
654&i2c3 {
655 clock-frequency = <400000>;
656 pinctrl-names = "default", "gpio";
657 pinctrl-0 = <&pinctrl_i2c3>;
658 pinctrl-1 = <&pinctrl_i2c3_gpio>;
659 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
660 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
661};
662
663/* Verdin I2C_1 */
664&i2c4 {
665 clock-frequency = <400000>;
666 pinctrl-names = "default", "gpio";
667 pinctrl-0 = <&pinctrl_i2c4>;
668 pinctrl-1 = <&pinctrl_i2c4_gpio>;
669 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
670 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
671
672 gpio_expander_21: gpio-expander@21 {
673 compatible = "nxp,pcal6416";
674 #gpio-cells = <2>;
675 gpio-controller;
676 reg = <0x21>;
677 vcc-supply = <&reg_3p3v>;
678 status = "disabled";
679 };
680
681 lvds_ti_sn65dsi83: bridge@2c {
682 compatible = "ti,sn65dsi83";
683 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
684 /* Verdin GPIO_10_DSI (SODIMM 21) */
685 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
688 reg = <0x2c>;
689 status = "disabled";
690 };
691
692 /* Current measurement into module VCC */
693 hwmon: hwmon@40 {
694 compatible = "ti,ina219";
695 reg = <0x40>;
696 shunt-resistor = <10000>;
697 status = "disabled";
698 };
699
700 hdmi_lontium_lt8912: hdmi@48 {
701 compatible = "lontium,lt8912b";
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
704 reg = <0x48>;
705 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
706 /* Verdin GPIO_10_DSI (SODIMM 21) */
707 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
708 status = "disabled";
709 };
710
711 atmel_mxt_ts: touch@4a {
712 compatible = "atmel,maxtouch";
713 /*
714 * Verdin GPIO_9_DSI
715 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
716 */
717 interrupt-parent = <&gpio4>;
718 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
721 reg = <0x4a>;
722 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame^]723 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]724 status = "disabled";
725 };
726
727 /* Temperature sensor on carrier board */
728 hwmon_temp: sensor@4f {
729 compatible = "ti,tmp75c";
730 reg = <0x4f>;
731 status = "disabled";
732 };
733
734 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
735 eeprom_display_adapter: eeprom@50 {
736 compatible = "st,24c02";
737 pagesize = <16>;
738 reg = <0x50>;
739 status = "disabled";
740 };
741
742 /* EEPROM on carrier board */
743 eeprom_carrier_board: eeprom@57 {
744 compatible = "st,24c02";
745 pagesize = <16>;
746 reg = <0x57>;
747 status = "disabled";
748 };
749};
750
751/* TODO: Verdin PCIE_1 */
752
753/* Verdin PWM_1 */
754&pwm1 {
755 pinctrl-names = "default";
756 pinctrl-0 = <&pinctrl_pwm_1>;
757 #pwm-cells = <3>;
758};
759
760/* Verdin PWM_2 */
761&pwm2 {
762 pinctrl-names = "default";
763 pinctrl-0 = <&pinctrl_pwm_2>;
764 #pwm-cells = <3>;
765};
766
767/* Verdin PWM_3_DSI */
768&pwm3 {
769 pinctrl-names = "default";
770 pinctrl-0 = <&pinctrl_pwm_3>;
771 #pwm-cells = <3>;
772};
773
774/* TODO: Verdin I2S_1 */
775
776/* TODO: Verdin I2S_2 */
777
778&snvs_pwrkey {
779 status = "okay";
780};
781
782/* Verdin UART_1 */
783&uart1 {
784 pinctrl-names = "default";
785 pinctrl-0 = <&pinctrl_uart1>;
786 uart-has-rtscts;
787};
788
789/* Verdin UART_2 */
790&uart2 {
791 pinctrl-names = "default";
792 pinctrl-0 = <&pinctrl_uart2>;
793 uart-has-rtscts;
794};
795
796/* Verdin UART_3, used as the Linux Console */
797&uart3 {
798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_uart3>;
800};
801
802/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
803&uart4 {
804 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_uart4>;
806};
807
808/* Verdin USB_1 */
809&usb3_phy0 {
810 vbus-supply = <&reg_usb1_vbus>;
811};
812
813&usb_dwc3_0 {
814 adp-disable;
815 dr_mode = "otg";
816 hnp-disable;
817 maximum-speed = "high-speed";
818 over-current-active-low;
819 pinctrl-names = "default";
820 pinctrl-0 = <&pinctrl_usb_1_id>;
821 srp-disable;
822};
823
824/* Verdin USB_2 */
825&usb3_phy1 {
826 vbus-supply = <&reg_usb2_vbus>;
827};
828
829&usb_dwc3_1 {
830 disable-over-current;
831 dr_mode = "host";
832};
833
834/* Verdin SD_1 */
835&usdhc2 {
836 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
837 assigned-clock-rates = <400000000>;
838 bus-width = <4>;
839 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
840 disable-wp;
841 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
842 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
843 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
844 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
845 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
846 vmmc-supply = <&reg_usdhc2_vmmc>;
847};
848
849/* On-module eMMC */
850&usdhc3 {
851 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
852 assigned-clock-rates = <400000000>;
853 bus-width = <8>;
854 non-removable;
855 pinctrl-names = "default", "state_100mhz", "state_200mhz";
856 pinctrl-0 = <&pinctrl_usdhc3>;
857 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
858 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
859 status = "okay";
860};
861
862&wdog1 {
863 fsl,ext-reset-output;
864 pinctrl-names = "default";
865 pinctrl-0 = <&pinctrl_wdog>;
866 status = "okay";
867};
868
869&iomuxc {
870 pinctrl_bt_uart: btuartgrp {
871 fsl,pins =
872 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
873 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
874 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
875 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
876 };
877
878 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
879 fsl,pins =
880 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
881 };
882
883 pinctrl_ecspi1: ecspi1grp {
884 fsl,pins =
885 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
886 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
887 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
888 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
889 };
890
891 /* Connection On Board PHY */
892 pinctrl_eqos: eqosgrp {
893 fsl,pins =
894 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
895 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
896 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
897 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
898 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
899 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
900 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
901 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
902 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
903 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
904 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
905 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
906 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
907 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
908 };
909
910 /* ETH_INT# shared with TPM_INT# (usually N/A) */
911 pinctrl_eth_tpm_int: ethtpmintgrp {
912 fsl,pins =
913 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
914 };
915
916 /* Connection Carrier Board PHY ETH_2 */
917 pinctrl_fec: fecgrp {
918 fsl,pins =
919 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
920 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
921 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
922 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
923 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
924 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
925 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
926 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
927 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
928 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
929 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
930 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
931 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
932 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
933 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
934 };
935
936 pinctrl_fec_sleep: fecsleepgrp {
937 fsl,pins =
938 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
939 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
940 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
941 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
942 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
943 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
944 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
945 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
946 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
947 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
948 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
949 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
950 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
951 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
952 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
953 };
954
955 pinctrl_flexcan1: flexcan1grp {
956 fsl,pins =
957 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
958 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
959 };
960
961 pinctrl_flexcan2: flexcan2grp {
962 fsl,pins =
963 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
964 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
965 };
966
967 pinctrl_flexspi0: flexspi0grp {
968 fsl,pins =
969 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
970 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
971 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
972 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
973 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
974 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
975 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
976 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
977 };
978
979 pinctrl_gpio1: gpio1grp {
980 fsl,pins =
981 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
982 };
983
984 pinctrl_gpio2: gpio2grp {
985 fsl,pins =
986 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
987 };
988
989 pinctrl_gpio3: gpio3grp {
990 fsl,pins =
991 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
992 };
993
994 pinctrl_gpio4: gpio4grp {
995 fsl,pins =
996 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
997 };
998
999 pinctrl_gpio5: gpio5grp {
1000 fsl,pins =
1001 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
1002 };
1003
1004 pinctrl_gpio6: gpio6grp {
1005 fsl,pins =
1006 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
1007 };
1008
1009 pinctrl_gpio7: gpio7grp {
1010 fsl,pins =
1011 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
1012 };
1013
1014 pinctrl_gpio8: gpio8grp {
1015 fsl,pins =
1016 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
1017 };
1018
1019 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1020 pinctrl_gpio_9_dsi: gpio9dsigrp {
1021 fsl,pins =
1022 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
1023 };
1024
1025 /* Verdin GPIO_10_DSI */
1026 pinctrl_gpio_10_dsi: gpio10dsigrp {
1027 fsl,pins =
1028 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1029 };
1030
1031 /* Non-wifi MSP usage only */
1032 pinctrl_gpio_hog1: gpiohog1grp {
1033 fsl,pins =
1034 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1035 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1036 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1037 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1038 };
1039
1040 /* USB_2_OC# */
1041 pinctrl_gpio_hog2: gpiohog2grp {
1042 fsl,pins =
1043 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1044 };
1045
1046 pinctrl_gpio_hog3: gpiohog3grp {
1047 fsl,pins =
1048 <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
1049 /* CSI_1_MCLK */
1050 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1051 };
1052
1053 /* Wifi usage only */
1054 pinctrl_gpio_hog4: gpiohog4grp {
1055 fsl,pins =
1056 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1057 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1058 };
1059
1060 pinctrl_gpio_keys: gpiokeysgrp {
1061 fsl,pins =
1062 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1063 };
1064
1065 pinctrl_hdmi_hog: hdmihoggrp {
1066 fsl,pins =
1067 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
1068 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
1069 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
1070 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
1071 };
1072
1073 /* On-module I2C */
1074 pinctrl_i2c1: i2c1grp {
1075 fsl,pins =
1076 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1077 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1078 };
1079
1080 pinctrl_i2c1_gpio: i2c1gpiogrp {
1081 fsl,pins =
1082 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1083 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1084 };
1085
1086 /* Verdin I2C_2_DSI */
1087 pinctrl_i2c2: i2c2grp {
1088 fsl,pins =
1089 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1090 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1091 };
1092
1093 pinctrl_i2c2_gpio: i2c2gpiogrp {
1094 fsl,pins =
1095 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1096 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1097 };
1098
1099 /* Verdin I2C_4_CSI */
1100 pinctrl_i2c3: i2c3grp {
1101 fsl,pins =
1102 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1103 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1104 };
1105
1106 pinctrl_i2c3_gpio: i2c3gpiogrp {
1107 fsl,pins =
1108 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1109 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1110 };
1111
1112 /* Verdin I2C_1 */
1113 pinctrl_i2c4: i2c4grp {
1114 fsl,pins =
1115 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1116 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1117 };
1118
1119 pinctrl_i2c4_gpio: i2c4gpiogrp {
1120 fsl,pins =
1121 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1122 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1123 };
1124
1125 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1126 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1127 fsl,pins =
1128 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1129 };
1130
1131 /* Verdin I2S_2_D_OUT shared with SAI3 */
1132 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1133 fsl,pins =
1134 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1135 };
1136
1137 pinctrl_pcie: pciegrp {
1138 fsl,pins =
1139 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1140 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1141 };
1142
1143 pinctrl_pmic: pmicirqgrp {
1144 fsl,pins =
1145 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1146 };
1147
1148 pinctrl_pwm_1: pwm1grp {
1149 fsl,pins =
1150 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1151 };
1152
1153 pinctrl_pwm_2: pwm2grp {
1154 fsl,pins =
1155 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1156 };
1157
1158 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1159 pinctrl_pwm_3: pwm3grp {
1160 fsl,pins =
1161 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1162 };
1163
1164 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1165 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1166 fsl,pins =
1167 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1168 };
1169
1170 pinctrl_reg_eth: regethgrp {
1171 fsl,pins =
1172 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1173 };
1174
1175 pinctrl_sai1: sai1grp {
1176 fsl,pins =
1177 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1178 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1179 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1180 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1181 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1182 };
1183
1184 pinctrl_sai3: sai3grp {
1185 fsl,pins =
1186 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1187 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1188 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1189 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1190 };
1191
1192 pinctrl_uart1: uart1grp {
1193 fsl,pins =
1194 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1195 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1196 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1197 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1198 };
1199
1200 pinctrl_uart2: uart2grp {
1201 fsl,pins =
1202 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1203 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1204 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1205 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1206 };
1207
1208 pinctrl_uart3: uart3grp {
1209 fsl,pins =
1210 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1211 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1212 };
1213
1214 /* Non-wifi usage only */
1215 pinctrl_uart4: uart4grp {
1216 fsl,pins =
1217 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1218 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1219 };
1220
1221 pinctrl_usb1_vbus: usb1vbusgrp {
1222 fsl,pins =
1223 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
1224 };
1225
1226 /* USB_1_ID */
1227 pinctrl_usb_1_id: usb1idgrp {
1228 fsl,pins =
1229 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1230 };
1231
1232 pinctrl_usb2_vbus: usb2vbusgrp {
1233 fsl,pins =
1234 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
1235 };
1236
1237 /* On-module Wi-Fi */
1238 pinctrl_usdhc1: usdhc1grp {
1239 fsl,pins =
1240 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1241 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1242 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1243 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1244 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1245 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1246 };
1247
1248 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1249 fsl,pins =
1250 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1251 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1252 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1253 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1254 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1255 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1256 };
1257
1258 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1259 fsl,pins =
1260 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1261 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1262 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1263 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1264 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1265 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1266 };
1267
1268 pinctrl_usdhc2_cd: usdhc2cdgrp {
1269 fsl,pins =
1270 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1271 };
1272
1273 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1274 fsl,pins =
1275 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1276 };
1277
1278 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1279 fsl,pins =
1280 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1281 };
1282
1283 pinctrl_usdhc2: usdhc2grp {
1284 fsl,pins =
1285 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1286 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1287 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1288 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1289 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1290 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1291 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1292 };
1293
1294 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1295 fsl,pins =
1296 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1297 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1298 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1299 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1300 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1301 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1302 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1303 };
1304
1305 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1306 fsl,pins =
1307 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1308 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1309 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1310 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1311 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1312 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1313 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1314 };
1315
1316 /* Avoid backfeeding with removed card power */
1317 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1318 fsl,pins =
1319 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1320 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1321 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1322 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1323 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1324 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1325 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1326 };
1327
1328 pinctrl_usdhc3: usdhc3grp {
1329 fsl,pins =
1330 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1331 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1332 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1333 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1334 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1335 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1336 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1337 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1338 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1339 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1340 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1341 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1342 };
1343
1344 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1345 fsl,pins =
1346 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1347 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1348 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1349 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1350 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1351 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1352 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1353 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1354 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1355 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1356 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1357 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1358 };
1359
1360 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1361 fsl,pins =
1362 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1363 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1364 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1365 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1366 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1367 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1368 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1369 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1370 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1371 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1372 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1373 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1374 };
1375
1376 pinctrl_wdog: wdoggrp {
1377 fsl,pins =
1378 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1379 };
1380
1381 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1382 fsl,pins =
1383 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1384 };
1385
1386 pinctrl_wifi_ctrl: wifictrlgrp {
1387 fsl,pins =
1388 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1389 };
1390
1391 pinctrl_wifi_i2s: wifii2sgrp {
1392 fsl,pins =
1393 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1394 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1395 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1396 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1397 };
1398
1399 pinctrl_wifi_pwr_en: wifipwrengrp {
1400 fsl,pins =
1401 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1402 };
1403};