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git01.mediatek.com / filogic / uboot / 109a8d3e7538b9d2e64e6b2cdc532d429216816b / . / board / freescale / p1022ds / tlb.c
blob: 71e71f70703961d47ecce6ddc3baa055300df15a [file] [log] [blame]
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500[diff] [blame]1/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 */
11
12#include <common.h>
13#include <asm/mmu.h>
14
15struct fsl_e_tlb_entry tlb_table[] = {
16 /* TLB 0 - for temp stack in cache */
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
21 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
25 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
26 MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
28 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
29 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
30 MAS3_SX|MAS3_SW|MAS3_SR, 0,
31 0, 0, BOOKE_PAGESZ_4K, 0),
32
33 /* TLB 1 */
34 /* *I*** - Covers boot page */
35 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
36 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
37 0, 0, BOOKE_PAGESZ_4K, 1),
38
39 /* *I*G* - CCSRBAR */
40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42 0, 1, BOOKE_PAGESZ_1M, 1),
43
44 /* W**G* - Flash/promjet, localbus */
45 /* This will be changed to *I*G* after relocation to RAM. */
46 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
47 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
48 0, 2, BOOKE_PAGESZ_256M, 1),
49
50 /* *I*G* - PCI */
51 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
52 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
53 0, 3, BOOKE_PAGESZ_1G, 1),
54
55 /* *I*G* - PCI */
56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
57 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 4, BOOKE_PAGESZ_256M, 1),
60
61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
62 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 0, 5, BOOKE_PAGESZ_256M, 1),
65
66 /* *I*G* - PCI I/O */
67 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
69 0, 6, BOOKE_PAGESZ_256K, 1),
70
71 SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 7, BOOKE_PAGESZ_4K, 1),
Matthew McClintockc4253e92012-05-18 06:04:17 +0000[diff] [blame]74
75#ifdef CONFIG_SYS_RAMBOOT
76 /* *I*G - eSDHC/eSPI/NAND boot */
77 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
78 MAS3_SX|MAS3_SW|MAS3_SR, 0,
79 0, 8, BOOKE_PAGESZ_1G, 1),
80
81 /* map the second 1G */
82 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
83 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85 0, 9, BOOKE_PAGESZ_1G, 1),
86#endif
87#
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500[diff] [blame]88};
89
90int num_tlb_entries = ARRAY_SIZE(tlb_table);