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wdenk12490652004-04-18 21:13:41 +00001/*
Michal Simek75348da2011-09-25 21:03:08 +00002 * (C) Copyright 2008-2011 Michal Simek <monstr@monstr.eu>
Michal Simek403d6192008-07-11 10:10:31 +02003 * Clean driver and add xilinx constant from header file
wdenk12490652004-04-18 21:13:41 +00004 *
Michal Simek403d6192008-07-11 10:10:31 +02005 * (C) Copyright 2004 Atmark Techno, Inc.
wdenk12490652004-04-18 21:13:41 +00006 * Yasushi SHOJI <yashi@atmark-techno.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Michal Simek403d6192008-07-11 10:10:31 +020018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk12490652004-04-18 21:13:41 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
Michal Simek75348da2011-09-25 21:03:08 +000028#include <common.h>
Michal Simek403d6192008-07-11 10:10:31 +020029#include <asm/io.h>
Michal Simek75348da2011-09-25 21:03:08 +000030#include <linux/compiler.h>
31#include <serial.h>
wdenk12490652004-04-18 21:13:41 +000032
Michal Simek403d6192008-07-11 10:10:31 +020033#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
34#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
35#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
wdenk12490652004-04-18 21:13:41 +000036
Michal Simek75348da2011-09-25 21:03:08 +000037struct uartlite {
38 unsigned int rx_fifo;
39 unsigned int tx_fifo;
40 unsigned int status;
41};
42
43static const struct uartlite *userial_ports[4] = {
44#ifdef XILINX_UARTLITE_BASEADDR
45 [0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
46#endif
47#ifdef XILINX_UARTLITE_BASEADDR1
48 [1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
49#endif
50#ifdef XILINX_UARTLITE_BASEADDR2
51 [2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
52#endif
53#ifdef XILINX_UARTLITE_BASEADDR3
54 [3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
55#endif
56};
57
58void uartlite_serial_putc(const char c, const int port)
59{
60 struct uartlite *regs = userial_ports[port];
61
62 if (c == '\n')
63 uartlite_serial_putc('\r', port);
64
65 while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
66 ;
67 out_be32(&regs->tx_fifo, c & 0xff);
68}
69
70void uartlite_serial_puts(const char *s, const int port)
71{
72 while (*s)
73 uartlite_serial_putc(*s++, port);
74}
75
76int uartlite_serial_getc(const int port)
77{
78 struct uartlite *regs = userial_ports[port];
79
80 while (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
81 ;
82 return in_be32(&regs->rx_fifo) & 0xff;
83}
84
85int uartlite_serial_tstc(const int port)
86{
87 struct uartlite *regs = userial_ports[port];
wdenk12490652004-04-18 21:13:41 +000088
Michal Simek75348da2011-09-25 21:03:08 +000089 return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
90}
91
92#if !defined(CONFIG_SERIAL_MULTI)
wdenk12490652004-04-18 21:13:41 +000093int serial_init(void)
94{
95 /* FIXME: Nothing for now. We should initialize fifo, etc */
96 return 0;
97}
98
99void serial_setbrg(void)
100{
101 /* FIXME: what's this for? */
102}
103
104void serial_putc(const char c)
105{
Michal Simek75348da2011-09-25 21:03:08 +0000106 uartlite_serial_putc(c, 0);
wdenk12490652004-04-18 21:13:41 +0000107}
108
Michal Simek75348da2011-09-25 21:03:08 +0000109void serial_puts(const char *s)
wdenk12490652004-04-18 21:13:41 +0000110{
Michal Simek75348da2011-09-25 21:03:08 +0000111 uartlite_serial_puts(s, 0);
wdenk12490652004-04-18 21:13:41 +0000112}
113
114int serial_getc(void)
115{
Michal Simek75348da2011-09-25 21:03:08 +0000116 return uartlite_serial_getc(0);
wdenk12490652004-04-18 21:13:41 +0000117}
118
119int serial_tstc(void)
120{
Michal Simek75348da2011-09-25 21:03:08 +0000121 return uartlite_serial_tstc(0);
122}
123#endif
124
125#if defined(CONFIG_SERIAL_MULTI)
126/* Multi serial device functions */
127#define DECLARE_ESERIAL_FUNCTIONS(port) \
128 int userial##port##_init(void) \
129 { return(0); } \
130 void userial##port##_setbrg(void) {} \
131 int userial##port##_getc(void) \
132 { return uartlite_serial_getc(port); } \
133 int userial##port##_tstc(void) \
134 { return uartlite_serial_tstc(port); } \
135 void userial##port##_putc(const char c) \
136 { uartlite_serial_putc(c, port); } \
137 void userial##port##_puts(const char *s) \
138 { uartlite_serial_puts(s, port); }
139
140/* Serial device descriptor */
141#define INIT_ESERIAL_STRUCTURE(port, name) {\
142 name,\
143 userial##port##_init,\
144 NULL,\
145 userial##port##_setbrg,\
146 userial##port##_getc,\
147 userial##port##_tstc,\
148 userial##port##_putc,\
149 userial##port##_puts, }
150
151DECLARE_ESERIAL_FUNCTIONS(0);
152struct serial_device uartlite_serial0_device =
153 INIT_ESERIAL_STRUCTURE(0, "ttyUL0");
154DECLARE_ESERIAL_FUNCTIONS(1);
155struct serial_device uartlite_serial1_device =
156 INIT_ESERIAL_STRUCTURE(1, "ttyUL1");
157DECLARE_ESERIAL_FUNCTIONS(2);
158struct serial_device uartlite_serial2_device =
159 INIT_ESERIAL_STRUCTURE(2, "ttyUL2");
160DECLARE_ESERIAL_FUNCTIONS(3);
161struct serial_device uartlite_serial3_device =
162 INIT_ESERIAL_STRUCTURE(3, "ttyUL3");
163
164__weak struct serial_device *default_serial_console(void)
165{
166# ifdef XILINX_UARTLITE_BASEADDR
167 return &uartlite_serial0_device;
168# endif /* XILINX_UARTLITE_BASEADDR */
169# ifdef XILINX_UARTLITE_BASEADDR1
170 return &uartlite_serial1_device;
171# endif /* XILINX_UARTLITE_BASEADDR1 */
172# ifdef XILINX_UARTLITE_BASEADDR2
173 return &uartlite_serial2_device;
174# endif /* XILINX_UARTLITE_BASEADDR2 */
175# ifdef XILINX_UARTLITE_BASEADDR3
176 return &uartlite_serial3_device;
177# endif /* XILINX_UARTLITE_BASEADDR3 */
wdenk12490652004-04-18 21:13:41 +0000178}
Michal Simek75348da2011-09-25 21:03:08 +0000179#endif /* CONFIG_SERIAL_MULTI */